UART Flow Control · protocols

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What you'll learn

UART is asynchronous serial — baud tolerance, FIFO depth, and flow control determine reliability.

Frame: start bit, configured data width/order, optional parity, and stop interval.
Baud mismatch budget depends on frame format, receiver sampling and clock error at both endpoints.
Hardware flow control (RTS/CTS) or software (XON/XOFF).

Connection

Simplest async protocol — FIFO and interrupt timing issues appear everywhere.

Key diagram

Receive headroom has two consumers

Receive headroom has two consumers. The UART worked example separately budgets character time, service latency and sender stop latency. Flow control is not an instantaneous eraser of in-flight data.

The UART worked example separately budgets character time, service latency and sender stop latency. Flow control is not an instantaneous eraser of in-flight data.

Check yourself Why can the free-slot count not all be assigned to interrupt latency?

Some slots must cover characters that can still arrive before the remote sender stops.

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