Read first: Read the mechanism and worked trace first
A controller logs a failed read. Observe actual SDA/SCL at the target pins, then relate the failure to address, data and acknowledgement phases. A software timeout is not itself a decoded NACK.
Tell a NACK from a clock that never rose — decision record
Apply the stated local assumptions; record actual platform values before using this as an implementation checklist.
Decision / observation | Required evidence | Consequence |
|---|---|---|
Ninth SCL pulse occurs; SDA high | Receiver did not acknowledge that byte | Identify whether the receiver was target or controller |
SCL stays low after release | Target stretching or another electrical/drive condition | Inspect actual line ownership and supported timeout policy |
Rise is too slow at selected speed | Pull-up, capacitance and mode limits | Do not repair an electrical timing failure by changing the register address |
A NACK requires the applicable acknowledgement clock with SDA released high. A clock that never rises is a different observation and needs line/timing investigation.
Pull-up selection depends on bus capacitance, required rise time and participant sink capability. Added devices often add capacitance, but simply lowering resistance can violate low-level current or VOL limits; calculate and measure both bounds.
Firmware must match the target address (often influenced by strap pins), supported bus mode and register map. Two targets responding to the same address can both acknowledge; later read data or command interpretation may conflict rather than producing a reliable NACK.
Verify pull-ups on board schematic — missing pull-ups = no communication.
Reset sequence: device must be out of reset before I2C access.
Shared segment: ensure simultaneously enabled targets do not respond to the same address unless a mux, enable or other selection scheme isolates them.