APB is a useful choice for GPIO, timer and UART control registers. AHB-Lite can serve a modest pipelined subsystem. AXI4-Lite offers register accesses through AXI-style channels. Full AXI4 supports bursts and multiple outstanding traffic streams. Match the endpoint and fabric contracts rather than treating one protocol as a mandatory replacement for another.
Estimate the required useful bytes/s and access latency before choosing a bridge. An APB control path may be entirely adequate while the same peripheral's bulk DMA data uses a different interface. Include bridge buffering, clock crossings and target wait states in the latency budget.
APB itself needs at least setup plus access; upstream bridge/crossing latency is additional and measured in the relevant clock domains.
Clock gating requires an agreed wake/admission policy so the selected target can observe setup and eventually complete its access.
Define an error/default response for unmapped addresses; an incomplete decode must not silently leave a requester waiting forever.