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Course contents

  • How to Use This Course
  • Protocol Metrics Reference
  • Protocols Glossary
  • Reading Path
  • Protocol Fundamentals25
  • AMBA Family (APB / AHB / AXI)17
  • Coherence Fabrics (ACE / CHI)17
  • Memory Interfaces (DDR / LPDDR / HBM)17
    • DDR Controller / PHY Split
    • Training & Timing Modes
    • Refresh & Bandwidth Efficiency
    • Memory Interface Debug
      • Memory Interface Debug: Concepts
      • Memory Interface Debug: Integration
      • Memory Interface Debug: Debug
      • Memory Interface Debug: Interview
    • Memory Interfaces (DDR / LPDDR / HBM): Tricky Q&A
  • PCIe & CXL17
  • Embedded Peripherals (I2C / SPI / UART)17
  • High-Speed I/O (USB / Ethernet / MIPI)17
  • Protocol Verification & Compliance21
  • Protocols Interview Prep5
  • Interface Protocols Cheatsheet
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←Memory Interface Debug
  1. Topics
  2. Bus Protocols
  3. Memory Interfaces (DDR / LPDDR / HBM)
  4. Memory Interface Debug
  5. Memory Interface Debug: Integration
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    Interface ProtocolsAll levels

    Memory Interface Debug: Integration

    Integration for Memory Interface Debug.

    Integration in practice

    Preserve enough context for another engineer to replay the failure

    Read first: Read the mechanism and worked trace first

    A reproducible memory failure report must distinguish workload, configuration and observation. “Memory test failed after boot” cannot reveal whether two machines ran the same work.

    Preserve enough context for another engineer to replay the failure — decision record

    Apply the stated local assumptions; record actual platform values before using this as an implementation checklist.

    Decision / observation

    Required evidence

    Consequence

    Configuration

    Part/mode, active timings, clock, mapping and training result

    A nominal data rate alone is insufficient

    Workload

    Initial data, access sequence, address range and concurrency

    Preserve failing byte/address and sequence identity

    Conditions

    Temperature/voltage observations and reset history

    Avoid comparing different corners as if only firmware changed

    Result

    First mismatch, command/lane evidence and performed work

    A passing shorter run is not an equivalent replay

    Check yourself What should accompany a proposed fix that only reports “test passed”?

    The configuration, workload, conditions, performed work and checked result, compared with the failing replay. Otherwise the result may not exercise the original failure.

    Cross-team memory debug

    Memory debug involves silicon (controller/PHY), firmware (training, MRW), board (SI, routing), and software (address map, cache policy). The review memo must name which layer owns the evidence.

    • SI team: eye diagrams, channel loss, crosstalk.

    • Firmware: training sequence, mode registers, QoS settings.

    • Software: memory attributes, DMA buffer alignment, interleave.

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    See also

    • Memory Interface Debug: Interview