In a common non-inverted UART format, idle is high and a low start bit is followed by configured data bits, optional parity and a high stop interval. Many UARTs send the least-significant data bit first, but framing options and polarity are implementation/configuration contracts.
A receiver qualifies the start bit and samples according to its own clocking algorithm; oversampling by 16 is common but not universal. Allowable transmitter/receiver baud mismatch depends on sample placement, frame length, resynchronisation behaviour, jitter and both clock errors, so use the controller/device specification rather than a universal ±3% rule.
Frame time and receive-service budget
Illustrative non-inverted 8N1 UART at exactly 115,200 baud: one start, eight data, no parity, one stop bit; LSB first. A separate illustrative receiver has a 16-character FIFO and raises service at occupancy 8. It has room for eight more characters. Assume no draining until the service completes and conservatively allow two extra in-flight characters beyond arrivals counted during that delay.
Quantity / case | Calculation | Consequence |
|---|---|---|
Bits per character | 1 + 8 + 0 + 1 = 10 | Do not budget as eight bit-times per byte. |
Character interval | 10 / 115,200 ≈ 86.81 µs | Payload rate is 11,520 bytes/s without gaps. |
Service delay 300 µs | ceil(300/86.81) + 2 = 6 arrivals | Within the eight free slots under this bound. |
Service delay 600 µs | ceil(600/86.81) + 2 = 9 arrivals | Exceeds eight slots: overrun is possible before service. |
No. The worst-case bound admits nine more characters into eight slots. Reduce the worst-case delay or trigger earlier, add effective flow control/buffering, or reduce arrival rate. Average ISR latency does not establish the worst-case capacity guarantee.
Compute actual baud from the documented input-clock, oversampling and divisor relationship; fractional dividers and fixed prescalers differ by controller.
FIFO depth determines how long the CPU can ignore the UART.
Overrun: an arriving character cannot be retained because the receiver holding register/FIFO has no available capacity under that implementation's policy.
Hardware flow control commonly uses RTS/CTS, but signal direction, polarity and automatic FIFO-threshold behaviour depend on DTE/DCE wiring and the UART implementation. Confirm what the local controller calls RTS and when the remote transmitter must stop; account for bytes already in flight.
Software flow control reserves control characters such as XON/XOFF in the byte stream. Arbitrary binary payload needs an agreed escaping/framing rule or software flow control disabled; it is not inherently impossible, but raw unescaped bytes can be misinterpreted.
Size receive service from FIFO capacity, trigger level, worst-case service latency, frame bits per character and bytes already in flight.
TX starvation may insert idle gaps between complete frames; whether it reports underrun or breaks a higher-level deadline depends on the controller and framing contract.
Console UART in boot: polling mode avoids interrupt setup complexity.