Setup: Isolated caching-system example, not the core SRAM/APB system: CPU writes a buffer, then publishes work to DMA under a platform contract requiring coherent access. DMA reads zeros despite a newer dirty CPU value. Local handshake checks report no violation.
Tag CPU write txn: id=2 addr=0x8000_1000. Tag DMA read txn: id=7 addr=0x8000_1000.
Check CPU write cacheable/shareable attributes on AW channel.
Trace path: CPU -> L2 -> interconnect -> DRAM. DMA path: DRAM direct.
Under the stated non-coherent DMA model, discover that the bridge changes the attribute/domain so the CPU's dirty cache line is not observed by the DMA path.
Apply the platform DMA API's direction-specific ownership/cache-maintenance contract, use a suitable non-cacheable allocation, or provide a correctly configured hardware-coherent path; do not prescribe a generic clean-plus-invalidate sequence.
Outcome: For this defined model, the bridge changed the coherency contract. The repair must align allocation, DMA ownership/cache maintenance and hardware participation with the platform specification.
Lesson: Locally legal handshakes do not establish that two agents observe the same data version; trace the attribute and ownership contract end to end.
Setup: CPU0 intends a 32-bit LEN_BYTES write at 0x4000_0008, but adjacent CONTROL at 0x4000_000C changes unexpectedly. The upstream 64-bit W beat enables only lanes 0–3 with WSTRB=0x0F. This is a deliberately faulty width-conversion example, not legal register merging.
Capture AW address/size/length and accepted WDATA/WSTRB rather than inferring width from the physical bus.
Retain the original low four enabled bytes as the bridge command; upper WDATA lanes are disabled for this write.
Compare completing APB accesses with that command. In the planted fault the converter emits an extra write to CONTROL using disabled upper bytes.
Locate the first boundary that creates the extra access; do not change the register model to accept unintended side effects.
Replay varied disabled upper bytes and concurrent traffic, requiring exactly one LEN_BYTES completion and no CONTROL write.
Outcome: The conversion must preserve the original enabled byte range and target side effects. A 64-bit upstream bus does not authorise a second 32-bit peripheral write.
Lesson: Transaction layer includes access width and byte enables — not just address.