Networking OSI layers and silicon protocol layers rhyme but don't map 1:1. Silicon 'transaction layer' is closest to OSI session/presentation: it defines what the transfer means. Channel layer is transport: reliable delivery mechanics. Physical is physical. The useful habit from OSI: never debug a high-layer symptom by tweaking a low layer without evidence.
Two fundamental transaction shapes appear everywhere. Request/response (AXI, PCIe mem rd/wr): address + completion. Streaming (AXI-Stream, PCIe streaming, video pipelines): ordered data without per-beat addresses. Layering still applies — streams have packet boundaries (TLAST), flow control, and sideband (TUSER) at the transaction layer even without addresses.
Count the accepted work for each interface
Interface comparison outside reset. Stream sidebands are present only when the agreed interface implements them.
Boundary | Request/response read | Packet stream |
|---|---|---|
Admission | Address request accepted | Each data beat accepted by VALID and READY |
Correlation | Observed port, ID and retained request context | Agreed stream/packet context; TID only if implemented |
End of work | Expected accepted data and response, with the applicable final indication | Accepted final beat carrying TLAST when that packet convention is used |
Stall | Pending response/data remains retained | Data, byte qualifiers and final flag remain retained |
What to notice
A presented last flag does not finish work until its beat is accepted.
Optional stream identifiers cannot be assumed to exist on every interface.
The end-of-work and stall rows: the final beat must be accepted. A retained offer is not another received beat or a completed packet.
Clock-domain crossings and reset sequencing are integration boundaries. A multi-bit protocol transaction normally crosses through a protocol-aware asynchronous structure; synchronised Gray-coded pointers may be part of an asynchronous FIFO, but are not themselves a general transaction transport. If a master admits work before the destination path is available, the design needs an explicit hold, retry, error or recovery contract.
CDC: use protocol-aware FIFOs (AXI CDC), not ad-hoc valid/ready sync.
Reset order: document which blocks must be alive before masters issue.
Power transition: define quiesce, rejection, retention, isolation and recovery behaviour for in-flight and newly offered transactions.