CPOL=0 means the clock idles low; CPOL=1 means it idles high. In the conventional four-mode naming, CPHA selects whether capture occurs on the first or second clock transition after chip select. Confirm the controller's terminology and the device timing diagram rather than relying only on a mode number.
Data shifts on one edge, samples on the opposite. MOSI (master out) and MISO (master in) shift simultaneously — full duplex. MSB or LSB first is device-specific.
Mode 0: follow two bits before extrapolating to a byte
Illustrative MSB-first 0x96. CS is active, SCLK starts low, D7=1 is set up before the first rising edge. Each row is an edge event; setup/hold durations come from the selected target specification.
Event | SCLK | MOSI | Receiver / transmitter action |
|---|---|---|---|
Before first rise | Low | D7 = 1 | Transmitter has already prepared the first bit. |
First rise | 0 → 1 | Still D7 = 1 | Receiver samples 1; transmitter does not change this bit on the sample edge. |
First fall | 1 → 0 | Prepare D6 = 0 | Transmitter changes for the next sample. |
Second rise | 0 → 1 | Still D6 = 0 | Receiver samples 0. |
Conventional SPI mode mapping
Four-mode naming as illustrated by Microchip TB3215, DS90003215C. This maps clock edges only; the selected target still defines word length, bit order, CS timing, dummy clocks and supported modes. Leading means first transition away from idle, trailing means return towards idle.
Mode | CPOL / CPHA | Idle | Sample | Shift / prepare next bit |
|---|---|---|---|---|
0 | 0 / 0 | Low | Leading: rising | Trailing: falling; first bit prepared before leading edge. |
1 | 0 / 1 | Low | Trailing: falling | Leading: rising. |
2 | 1 / 0 | High | Leading: falling | Trailing: rising; first bit prepared before leading edge. |
3 | 1 / 1 | High | Trailing: rising | Leading: falling. |
CS must satisfy the target's setup time and the first bit, bit 7=1, must satisfy data setup for that rising sampling edge. Waiting until that same edge to launch bit 7 is not the Mode 0 timing contract.
CS must be active (low for active-low) before the first clock edge and remain active through the transfer. CS deassert too early = truncated transfer. Setup time between CS assert and first clock varies by device.
Some devices require CS high between transactions. Others allow back-to-back with CS held low. Flash devices often need specific CS timing for deep power-down entry/exit.
CS polarity: active-low is common but not universal.
Multi-slave: separate CS per device, shared CLK/MOSI/MISO.
For a flash command that requires command/address/dummy/data under one CS assertion, preserve that envelope; phase lengths and lane usage come from the selected command and device.