Read first: Read the mechanism and worked trace first
CPU and a non-coherent device exchange one streaming-mapped buffer. The direction of transfer, mapping lifetime and ownership are specified by the OS/platform DMA API; this exercise does not prescribe raw cache instructions.
Write the buffer handover before adding maintenance calls — decision record
Apply the stated local assumptions; record actual platform values before using this as an implementation checklist.
Decision / observation | Required evidence | Consequence |
|---|---|---|
CPU prepares device input | CPU writes are published under the DMA mapping/sync contract | Device must not read stale cached memory |
Device produces CPU input | Device completion plus platform sync-for-CPU contract | CPU must not consume stale data or race a live writer |
Buffer reused or unmapped | No outstanding device access; matching lifecycle | Premature reuse can corrupt unrelated later work |
No. Ordering a CPU’s operations does not by itself make the required bytes visible across a non-coherent path. Use the platform DMA lifecycle and ownership rules.
Hardware coherence does not replace publication ordering, ownership, access control or architecture rules for changing memory attributes. For DMA mapping, remapping and boot-stage handoff, follow the platform interfaces and transition sequence; some coherent paths need no explicit data-cache maintenance for ordinary transfers, while other transitions do.
CPU-to-device streaming-buffer ownership
An isolated non-coherent DMA example using the Linux DMA API contract, not raw cache instructions. Initially the CPU owns the buffer; no agent accesses it concurrently outside the contract. API error handling and device completion are required.
Stage | Allowed action | Evidence before moving on |
|---|---|---|
CPU owns | CPU fills payload | Writes complete according to the CPU/platform contract. |
Map for device read | Use DMA_TO_DEVICE mapping, or the specified synchronisation for a retained mapping | Mapping succeeds; use the returned DMA address, not the CPU virtual address. |
Publish / start | Prepare the descriptor and notify the device using the driver's ordering contract | Device observes valid work after the payload is ready. |
Device owns | Device reads; CPU does not modify the streaming buffer | Observe completion using the device-defined mechanism. |
Return ownership | Unmap, or synchronise for CPU as specified for the retained mapping | Only then reuse the buffer; do not equate a submitted request with completion. |
No. The device owns the active buffer until completion and the required return-of-ownership step. Coherent descriptors or a fast doorbell do not grant concurrent CPU writes to a streaming buffer.
Document which memory regions are hardware-coherent vs software-managed.
DMA allocation/mapping must satisfy the platform's granule, alignment, attribute and ownership requirements.
Bootloader-to-kernel handoff must define visibility, attributes and required maintenance/synchronisation for each region.