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Course contents

  • How to Use This Course
  • Protocol Metrics Reference
  • Protocols Glossary
  • Reading Path
  • Protocol Fundamentals25
  • AMBA Family (APB / AHB / AXI)17
  • Coherence Fabrics (ACE / CHI)17
    • ACE Coherent Transactions
    • Snoop & Cache Maintenance
    • CHI Topology Basics
      • CHI Topology Basics: Concepts
      • CHI Topology Basics: Integration
      • CHI Topology Basics: Debug
      • CHI Topology Basics: Interview
    • Coherence Fabric Debug
    • Coherence Fabrics (ACE / CHI): Tricky Q&A
  • Memory Interfaces (DDR / LPDDR / HBM)17
  • PCIe & CXL17
  • Embedded Peripherals (I2C / SPI / UART)17
  • High-Speed I/O (USB / Ethernet / MIPI)17
  • Protocol Verification & Compliance21
  • Protocols Interview Prep5
  • Interface Protocols Cheatsheet
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←Coherence Fabrics (ACE / CHI)
  1. Topics
  2. Bus Protocols
  3. Coherence Fabrics (ACE / CHI)
  4. CHI Topology Basics
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    Interface ProtocolsAll levels

    CHI Topology Basics

    CHI scales coherency to many cores with separate request, response, data, and snoop networks.

    • 4topics
    • 4lessons

    What you'll learn

    CHI scales coherency to many cores with separate request, response, data, and snoop networks.

    • CHI nodes: RN (Requester), HN (Home), SN (Subordinate); establish each node's supported capabilities.

    • REQ, RSP, DAT and SNP separate message roles; progress still needs correct dependencies and resource handling.

    • A coherent home may use a directory or snoop filter; do not assume every CHI system has one.

    Connection

    Compare ACE's channels with CHI's message roles. The specialist Cache Coherency course develops transient states and resource dependencies in depth.


    Key diagram

    CHI node roles, not a cycle budget

    CHI node roles, not a cycle budget. Generic role-level view within the lesson's named CHI revision. The selected transaction determines which branches are required; no fixed hop latency is implied.
    Generic role-level view within the lesson's named CHI revision. The selected transaction determines which branches are required; no fixed hop latency is implied.
    Check yourself Must every coherent transaction use both branches?

    No. Tracked state and transaction type determine the snoop and memory obligations.


    Study this topic

    1. Concepts — rules and mental models

    2. Integration — system contracts

    3. Debug — trace the first divergence

    4. Interview — explain and defend your answer

    PreviousNext: CHI Topology Basics: Concepts

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    Up nextCHI Topology Basics: Concepts

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    See also

    • ACE Coherent Transactions
    • Snoop & Cache Maintenance
    • Coherence Fabric Debug