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Course contents

  • How to Use This Course
  • Protocol Metrics Reference
  • Protocols Glossary
  • Reading Path
  • Protocol Fundamentals25
  • AMBA Family (APB / AHB / AXI)17
  • Coherence Fabrics (ACE / CHI)17
    • ACE Coherent Transactions
      • ACE Coherent Transactions: Concepts
      • ACE Coherent Transactions: Integration
      • ACE Coherent Transactions: Debug
      • ACE Coherent Transactions: Interview
    • Snoop & Cache Maintenance
    • CHI Topology Basics
    • Coherence Fabric Debug
    • Coherence Fabrics (ACE / CHI): Tricky Q&A
  • Memory Interfaces (DDR / LPDDR / HBM)17
  • PCIe & CXL17
  • Embedded Peripherals (I2C / SPI / UART)17
  • High-Speed I/O (USB / Ethernet / MIPI)17
  • Protocol Verification & Compliance21
  • Protocols Interview Prep5
  • Interface Protocols Cheatsheet
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←Coherence Fabrics (ACE / CHI)
  1. Topics
  2. Bus Protocols
  3. Coherence Fabrics (ACE / CHI)
  4. ACE Coherent Transactions
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    Interface ProtocolsAll levels

    ACE Coherent Transactions

    ACE adds coherent transaction and snoop mechanisms to AXI; correct domains, ordering and software contracts are still required for agents to share cacheable memory.

    • 4topics
    • 4lessons

    What you'll learn

    ACE adds coherent transaction and snoop mechanisms to AXI; correct domains, ordering and software contracts are still required for agents to share cacheable memory.

    • ACE extends AXI with AC (snoop addr), CR (snoop resp), CD (snoop data) channels.

    • Shareability domains define which masters participate in coherency.

    • A coherent home/interconnect uses transaction type, domain and tracked state to determine which snoop or memory actions are required.

    Connection

    Survey branch after AXI handshakes. Read the cache-state lesson first if MESI is new; use the specialist Cache Coherency course for controller construction.


    Key diagram

    Dirty peer supplies the newest value

    Dirty peer supplies the newest value. The lesson starts with dirty C0 data 7 and memory 0. CR and CD are distinct obligations; this figure does not impose their arrival order.
    The lesson starts with dirty C0 data 7 and memory 0. CR and CD are distinct obligations; this figure does not impose their arrival order.
    Check yourself Can IC use memory's 0 after the address was accepted?

    No. The dirty peer holds the newest 7, which the transaction must preserve while resolving permissions.


    Study this topic

    1. Follow a coherent read — Separate request, snoop response, data and completion.

    2. Choose the participating domain — Check the region and device contract before adding maintenance.

    3. Test a stale-data hypothesis — Collect the evidence that separates mapping, ordering and fabric faults.

    4. Explain false sharing — Distinguish extra traffic from an incorrect value.

    PreviousNext: ACE Coherent Transactions: Concepts

    Up next

    Up nextACE Coherent Transactions: Concepts

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    See also

    • Snoop & Cache Maintenance
    • CHI Topology Basics
    • Coherence Fabric Debug