For ordinary AXI4 at one interface, same ARID preserves read-response order and same AWID preserves write-response order. Different IDs permit additional reordering, but R and B remain distinct streams. Equal IDs alone do not provide read-after-write visibility. Bridges must retain the original association and legal order, while software follows its architecture/platform publication contract.

Common trap: Claiming AXI is globally ordered or reads/writes are serialized.

Start with required requests/s multiplied by matching-boundary average latency to estimate average concurrency. Then account for burstiness, tail latency, admission and return-buffer limits. Measure the same workload while varying capacity; a stalled AR channel alone does not prove that increasing master depth helps. ID values and total tracking entries are separate resources.

Common trap: Maximum outstanding without workload analysis.

A protocol-defined ordering operation with a particular scope, access class and completion meaning. Base AXI4 has no universal barrier transaction. Where an ACE revision supports barriers, follow that revision's exact domain and response rules; do not treat them as a global drain of all traffic or as identical to a CPU fence, cache maintenance operation or software lock.

Common trap: Confusing with CPU fence only — hardware barriers exist too.