Name the architecture's published memory model and the access type, attributes and synchronisation used by the example. Memory-type/cacheability/shareability attributes and a memory consistency model are related contracts, not interchangeable categories. The scoped SC versus x86-TSO store-buffer example below illustrates one ordering distinction; it is not a complete ranking or specification of every ISA. Follow the specialist memory-model lessons for deeper treatment.
Consider the Store Buffering test with distinct locations A=B=0 initially, one atomic aligned access per operation, no fences, no other writes and no compiler transformation. Core 0 stores A=1 then loads B into r0; core 1 stores B=1 then loads A into r1. Under sequential consistency (SC), (0,0) is forbidden: each zero read would have to precede the other core's store, creating a cycle when combined with the two program orders. The other three binary outcomes are allowed.
Under the x86-TSO store-buffer model for ordinary cacheable memory, (0,0) is allowed: each store can remain buffered while its core loads the other location's initial zero. The stores can drain afterwards without changing those read results. This distinguishes cross-location consistency from per-location coherence. Use assembly-level or explicitly defined model operations; ordinary racy non-atomic C/C++ is not a valid translation. See Sewell et al., x86-TSO: A Rigorous and Usable Programmer's Model for x86 Multiprocessors. Passing sampled executions does not prove a forbidden result can never occur.
Store buffering: state the model before judging the outcome
Initially A=B=0; two processors use abstract atomic accesses to ordinary cacheable memory, with no fences or other writers. These are model events, not non-atomic C/C++.
View | Processor 0 / model | Processor 1 / result |
|---|---|---|
Program | Store A=1; then r0=load B | Store B=1; then r1=load A |
SC | A single global order respects each program | Allowed: (0,1), (1,0), (1,1); not (0,0) |
x86-TSO store-buffer model | Stores can remain locally buffered | All four binary outcomes, including (0,0), are allowed |
Witness for (0,0) | Buffer A=1; load B before B's store drains | Buffer B=1; load A before A's store drains |
Finish witness | Drain buffered stores | A=B=1; both recorded read results remain 0 |
What to notice
The read results and final memory contents describe different points in the execution.
Coherence for each address does not supply SC ordering across A and B.
No. The loads happened before the other processor's buffered store became visible. Draining the stores later changes memory without rewriting the recorded load results.
For supported PCIe request types, Relaxed Ordering and ID-Based Ordering affect specific ordering permissions under the selected revision and capabilities. No Snoop concerns cache-snooping treatment, not a general completion fence. Do not assume every TLP supports every attribute, or that clearing RO establishes all CPU-to-device publication and completion requirements.
Check transaction-type-specific ordering rather than one global strong/relaxed label.
Enable relaxed ordering only where the requester, completer and software contract permit it.
A readback or completion wait has the guarantees of its documented path; it is not interchangeable with any barrier instruction.