AXI4 adds channel-specific rules on top of valid/ready. AW and W channels are independent in timing, so W can arrive before AW. W has no ID: write-data bursts follow AW request order without interleaving. R and B must match their pending read/write contexts and ordering rules. A master can offer AR while stalled on R; whether it can keep issuing requests depends on available tracking capacity.
Name the destination that is not accepting
AXI4 channel observations at one interface, outside reset. Every row means VALID=1 and READY=0 on the named channel; it does not identify the underlying root cause.
Channel | Retained offer | Destination not accepting |
|---|---|---|
AR | Read address/control | Read-request destination |
R | Read data/status | Read requester |
AW | Write address/control | Write-request destination |
W | Write data/strobes/final flag | Write-data destination |
B | Write response | Write requester |
What to notice
R and B flow towards the requester, unlike address and write-data channels.
Use the existing handshake/AXI simulation captures to study edge timing; this table classifies the observed stall.
No. It means the requester is not accepting offered read data at this interface. Refusing an offered read address is the AR row.
APB uses PREADY to extend the ACCESS phase, while its SETUP/ACCESS sequencing remains distinct from a generic ready/valid channel. AHB uses HREADY to extend the current transfer and therefore affects address/data pipeline progress. Compare their sampled acceptance rules rather than copying AXI dependencies into APB or AHB.
Measure bandwidth as accepted useful bytes divided by elapsed seconds. For fixed full-width beats, bytes/s = bytes_per_beat × clock_hz × accepted_beats / measured_cycles. If the conditional stall fraction is stalled_VALID_cycles / VALID_cycles, then accepted_cycles / measured_cycles = (VALID_cycles / measured_cycles) × (1 - conditional_stall_fraction). The offered-VALID fraction matters: idle cycles are not included in the conditional stall denominator.
Illustrative 100-cycle window: VALID is high for 90 cycles; 40 of those stall and 50 accept. At 8 bytes per beat and 1 GHz, 400 bytes transfer in 100 ns: 4 GB/s. The conditional stall fraction is 40/90, not 40/100. Doubling width would double bandwidth only if frequency, accepted-beat fraction and useful-lane utilisation stayed unchanged; it cannot overcome a fixed downstream bytes/s ceiling by itself.
Record idle, offered, stalled and accepted cycles over the same interval; handle a zero VALID denominator explicitly.
Count useful bytes on accepting edges, including write strobes when relevant.
Correlate stalls with occupancy and service events before attributing the limit to width, scheduling or acceptance.