Symptom: System throughput is 30% of expected. All channels show toggling activity. No protocol violations. Masters appear stalled ~60% of cycles.
Leading hypotheses: Possible causes include limited offered traffic, request capacity, downstream service and return backpressure. Activity alone does not establish transfer rate or rule out a width ceiling; count accepted useful bytes before choosing a hypothesis.
Per channel: compute conditional stall% = cycles(VALID && !READY) / cycles(VALID); report no offers when the VALID denominator is zero.
Identify worst channel — AR? W? separate read vs write paths.
Follow the request downstream from the stalled master, then follow responses back through interconnect and bridge boundaries.
Plot FIFO occupancy at bridge and slave ingress.
If memory slave: profile controller command queue depth and row policy.
If packet protocol: check credit counters per VC/type.
Change one suspected resource or policy at a time, compare the same replay and recheck the width-and-clock ceiling against the target.
Widening bus when ready stalls dominate.
Combinational valid = f(ready) — latent deadlock.
Ignoring per-channel stall breakdown (lumped 'bus busy').
Credit exhaustion misdiagnosed as endpoint hang.
Symptom: Chip passes simulation. FPGA prototype deadlocks on boot when DDR traffic starts.
Record actual source/destination clocks, reset release and the first accepted writes/reads; a lower prototype clock does not by itself imply insufficient FIFO capacity.
Check async FIFO full/empty flags during first DDR burst.
Verify the selected asynchronous FIFO's synchroniser, reset, flag and physical implementation constraints for the prototype technology.
Compare reset release order: simulation may release all at once.
Assuming sim-clean CDC works on FPGA without margin analysis.