List each agent's offered work, burst pattern, duty cycle and deadline, then identify shared bottlenecks under plausible simultaneous demand. Arbitration chooses who receives finite capacity; it cannot create bandwidth when mandatory aggregate demand exceeds that capacity. Change capacity, traffic scheduling or requirements when the budget is infeasible, and validate the chosen service guarantees.
Phase-aware budgeting: boot, idle, video playback, gaming, and ML inference have different traffic mixes. Size for the worst phase, verify all phases.
Row per master: name, width, clock, peak GB/s, typical duty, QoS class.
Row per bottleneck: DRAM channels, NoC links, PCIe x4 Gen4, etc.
Sweep offered load per phase and flag the point where a bandwidth or latency requirement first fails.
Reserve headroom justified by measured burstiness, coherency traffic, software variation and operating-corner uncertainty; record the assumptions rather than using a universal percentage.
Attach spreadsheet to architecture signoff.
Define classes and supported arbitration from the product's service requirements. Agent names do not establish urgency: a display DMA can have a hard deadline while a CPU background task does not. AXI AxQoS or internal source context may feed an implementation's policy; record that mapping and the assumptions needed for finite service and starvation avoidance.
Firmware QoS registers are part of the performance contract — document and test them.
CPU instruction fetch starvation: visible as IPC collapse.
Display underrun: visible as frame tears — real-time deadline miss.
PCIe traffic-class/virtual-channel mappings and arbitration are configured contracts, not an automatic priority guarantee from a TC number.