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How to Use This Course
Protocol Metrics Reference
Protocols Glossary
Reading Path
Protocol Fundamentals25
AMBA Family (APB / AHB / AXI)17
Coherence Fabrics (ACE / CHI)17
Memory Interfaces (DDR / LPDDR / HBM)17
PCIe & CXL17
Embedded Peripherals (I2C / SPI / UART)17
High-Speed I/O (USB / Ethernet / MIPI)17
Protocol Verification & Compliance21
Protocols Interview Prep5
Interface Protocols Cheatsheet

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←Protocols Interview Prep

Topics
Bus Protocols
Protocols Interview Prep
Scenario: DDR Bandwidth Collapse

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Interface ProtocolsAll levels

Scenario: DDR Bandwidth Collapse

A new traffic mix increases refresh stalls, row misses, and read/write turnarounds. The memory controller owner asks for more bus width.

Scenario

A new traffic mix increases refresh stalls, row misses, and read/write turnarounds. The memory controller owner asks for more bus width.

Metric

effective bandwidth drops from 42 GB/s to 21 GB/s on a video workload

Common pitfalls

Quote peak bandwidth
Ignore bank locality
Miss firmware QoS configuration

155 / 158

Next: Scenario: PCIe Link Degrade

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See also

Protocols Whiteboard Framework
Protocols Interview Q&A Bank