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Course contents

  • How to Use This Course
  • The NanoSoC Tour
  • Reading Path
  • SoC Glossary10
  • SoC Metrics Reference
  • SoC Cheatsheet
  • What SoC Integration Is12
  • Architecture and Budgets21
  • Memory Maps and Address Decode26
  • Interconnect and Bus Fabrics26
  • Clock and Reset Architecture24
  • Power Architecture21
  • Interrupts, DMA and Peripherals15
  • Memories, Boot and Security21
  • IP Integration and Handoff21
  • Top-Level Verification and Bring-up21
  • Package, Pads and I/O18
  • Chip Signoff and Tapeout18
  • SoC Interview Prep16
  • Capstone: Integrate NanoSoC19
    • Capstone Brief
    • Stage 1: Memory Map and Interconnect
    • Stage 2: Clocks, Resets, Power
      • Clock Plan and Crossing Inventory
      • Reset Tree and First-Fetch Evidence
      • Power Domains and Power-Up Evidence
    • Stage 3: Interrupts and Boot
    • Stage 4: Verification and Signoff
    • Solutions
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←Capstone: Integrate NanoSoC
  1. Topics
  2. SoC Design
  3. Capstone: Integrate NanoSoC
  4. Stage 2: Clocks, Resets, Power

Part 14 of 14Part 14 of 14/Capstone: Integrate NanoSoCAll levels

Stage 2: Clocks, Resets, Power

Challenge stage: observations, requirements and evidence before worked solutions.

  • 3topics
  • 3lessons

This is a Python model and manifest exercise. Work through the stage before opening Solutions: record your hypotheses and evidence first. The provided worked checks and fault injections appear after the solution key.

Lesson

After it you can...

Clock Plan and Crossing Inventory

Produce a clock table and a ten-row crossing table.

Reset Tree and First-Fetch Evidence

Produce a reset timeline and an annotated first-fetch trace.

Power Domains and Power-Up Evidence

Produce a power-boundary signal list and bus-access traces.

Suggested order: top to bottom, carrying each artefact into the next task. Use one baseline for every stage.

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See also

  • Capstone Brief
  • Stage 1: Memory Map and Interconnect
  • Stage 3: Interrupts and Boot