Terms are grouped by the subject where you meet them and listed alphabetically within each group. Each definition fixes the vocabulary the lessons use; the lesson in the last column teaches the idea. Where a term has two common meanings, the entry says which one the course uses. Numbers come from NanoSoC, the running chip of the course, and are teaching values, not figures for any real process or product.
Pair | The difference |
|---|---|
DECERR, SLVERR and PSLVERR | DECERR: nothing was there (no slave claimed the address). SLVERR: a slave was there and refused or failed the access. PSLVERR: the APB form of the slave error, which the bridge converts to SLVERR. |
Peak and sustained bandwidth | Peak is width times frequency. Sustained subtracts bubbles, arbitration and bridge cycles, and is the number a budget must use. |
Bandwidth and latency | Bandwidth is how much moves per second once data flows; latency is how long one access takes. A link can have plenty of one and little of the other. |
Phase-related and synchronous | Phase-related clocks keep an exact ratio. Signoff treats them as synchronous only if the offset between their trees is bounded and constrained; otherwise they are asynchronous. |
Reset assertion and release | Assertion may happen at any time. Release must be synchronised in each domain, because the release edge is what recovery and removal check. |
Isolation and retention | Isolation clamps a signal leaving a powered-down domain. Retention keeps a block's stored state while its main supply is off. A domain can need both. |
Clock gating and power gating | Clock gating stops switching and saves dynamic power; the state stays. Power gating removes supply and saves leakage too; the state is lost unless retained. |
Level and edge interrupt | A level stays asserted until its cause is cleared. An edge is a pulse that a slow receiver can miss. NanoSoC accepts levels only. |
RAW and PENDING | RAW is the synchronised input level. PENDING is RAW masked by ENABLE. |
Alias and hole | An alias has too many addresses for one thing. A hole has an address range with nothing behind it. |
Waiver and ECO | A waiver accepts a violation and leaves the design as it is. An ECO changes the design so the violation goes away. |
Block owner and integrator | The block owner is accountable for the block's own correctness. The integrator is accountable for everything between blocks: maps, wiring, clocks, resets, power and the evidence. |
SLVERR. The address is inside the APB window, so the interconnect sends it to the bridge; the slot decoder finds no slave in slot 7 and its default slave raises PSLVERR, which the bridge converts to SLVERR. DECERR is produced only when no slave at the interconnect claims the address, as in the holes below 0x4000_0000 and above 0x4000_FFFF.