You are the integrator for NanoSoC v1: one 32-bit core, a 2-master by 4-slave AXI4 fabric at 96 MHz, 64 KB plus 64 KB of SRAM, a 16 KB boot ROM, the streaming DMA behind its stream bridge, and five slow peripherals behind an APB bridge. This is a Python model and manifest exercise, not a full chip RTL run: the point is to make integration contracts executable and inspectable. Each stage produces one artefact, a map table, a clock and reset plan, an interrupt and boot record, a test matrix, and you write a checker against an independent requirement for each artefact. Complete the four challenge stages before opening Solutions, where the original runnable engine and all fault injections are provided for comparison. The lab ends with a signoff manifest check that reads every stage artefact and prints PASS only when every stage agrees, and a readiness review that lists what is still open, including a known hole in the security partition.
Topic | What it covers | After it you can... |
|---|---|---|
Requirements, deliverables, working data, rubric, the ten planted bugs | State what NanoSoC v1 must do and how the lab is graded. | |
Map table, decoder probes, response codes, link rates | Produce a checked map table and a link table. | |
Clock plan, ten crossings, reset tree, power domains, power-up | Produce a clock table, a reset timeline and a power-boundary list. | |
Interrupt map and latency, DMA driver trace, boot flow, secure partition | Produce an interrupt test log, a driver trace and a boot record. | |
Test matrix for all ten bugs, manifest, waiver ageing, final check | Run one script that prints PASS only when everything agrees. | |
Separated answer key after the checks: causes, fixes and closure evidence | Compare your diagnoses with the NanoSoC facts and record any open item. |
Suggested order: top to bottom, about 12 hours with the worked checks (NanoSoC teaching value: the Capstone Brief 1 hour, each stage 2 to 3 hours, signoff review 1 hour). The map comes first because every later stage quotes addresses; clocks, resets and power come as one stage because release order ties them together; interrupts and boot follow because the boot code programmes them; verification closes the lab because its matrix points back at every stage. Each challenge gives the required behaviour, observations to investigate and evidence to hand in. The separate Solutions topic provides the cause-and-fix key and all twelve runnable worked checks after your own investigation.
Per-stage checks pass against their own inputs, so a map fix that never reached the boot code would still show four green stages. The manifest cross-checks the artefacts against each other, which is the only check that catches drift between stages.