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Course contents

  • How to Use This Course
  • The NanoSoC Tour
  • Reading Path
  • SoC Glossary10
  • SoC Metrics Reference
  • SoC Cheatsheet
  • What SoC Integration Is12
  • Architecture and Budgets21
  • Memory Maps and Address Decode26
  • Interconnect and Bus Fabrics26
  • Clock and Reset Architecture24
  • Power Architecture21
  • Interrupts, DMA and Peripherals15
  • Memories, Boot and Security21
  • IP Integration and Handoff21
  • Top-Level Verification and Bring-up21
  • Package, Pads and I/O18
  • Chip Signoff and Tapeout18
  • SoC Interview Prep16
  • Capstone: Integrate NanoSoC19
    • Capstone Brief
    • Stage 1: Memory Map and Interconnect
    • Stage 2: Clocks, Resets, Power
      • Clock Plan and Crossing Inventory
      • Reset Tree and First-Fetch Evidence
      • Power Domains and Power-Up Evidence
    • Stage 3: Interrupts and Boot
    • Stage 4: Verification and Signoff
    • Solutions
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←Stage 2: Clocks, Resets, Power
  1. Topics
  2. SoC Design
  3. Capstone: Integrate NanoSoC
  4. Stage 2: Clocks, Resets, Power
  5. Clock Plan and Crossing Inventory
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    Part 14 of 14, lesson 6 of 19Part 14 of 14/Capstone: Integrate NanoSoC/Lesson 6 of 19All levels

    Clock Plan and Crossing Inventory

    Produce a clock table and a ten-row crossing table.

    The observation to investigate

    Collect the clock and crossing evidence for symptoms 2, 5, 6 and 10. Collect the evidence a reviewer would need beyond the frequencies.

    Required behaviour

    clk_per bypasses the PLL; requests and responses travel in opposite directions; crossing mechanisms require separate evidence.
    Capstone clocks and opposite AXI crossing directions

    What to notice. clk_per bypasses the PLL; requests and responses travel in opposite directions; crossing mechanisms require separate evidence.

    Check yourself Which branch survives when the PLL is off?

    The crystal bypass feeding clk_per at 24 MHz.

    Your investigation

    Write all ten crossing rows with source, receiver, width and mechanism. Compare the observed implementation with an independent requirement. Find and inject a fault that reproduces the relevant symptom, then state the structural evidence that rejects it.

    Inputs to start from

    • The clock and crossing tables in The NanoSoC Tour: crystal, PLL ratio, dividers, and the ten crossings X1 to X10.

    • The three clock domains (CPU, system, peripheral) and which blocks sit in each.

    • Symptoms 2, 5, 6 and 10 in the symptom table.

    Deliverable and pass criterion

    Deliverable. A clock table (source, divider, frequency for each of the three clocks) and a ten-row crossing table (ID, source clock, receiver clock, width, mechanism).

    Pass criterion. Each frequency derives from the crystal and the PLL ratio, the ten IDs are distinct, every row names a mechanism that suits its width, and the check rejects a table with one mechanism blank or mismatched.

    Evidence to hand in

    • The clock table with the arithmetic for each frequency.

    • The crossing table, plus the symptoms you think depend on a crossing and why.

    • The structural evidence (not a simulation run) that would show a crossing is safe.

    Keep your diagnosis in your own report. After the stage checks, compare it with Solutions and run the provided injection checks.

    Related topics

    • Next: Reset Tree and First-Fetch Evidence

    • NanoSoC reference tour

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    See also

    • Power Domains and Power-Up Evidence