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Course contents

  • How to Use This Course
  • The NanoSoC Tour
  • Reading Path
  • SoC Glossary10
  • SoC Metrics Reference
  • SoC Cheatsheet
  • What SoC Integration Is12
  • Architecture and Budgets21
  • Memory Maps and Address Decode26
  • Interconnect and Bus Fabrics26
  • Clock and Reset Architecture24
  • Power Architecture21
  • Interrupts, DMA and Peripherals15
  • Memories, Boot and Security21
  • IP Integration and Handoff21
  • Top-Level Verification and Bring-up21
  • Package, Pads and I/O18
  • Chip Signoff and Tapeout18
  • SoC Interview Prep16
  • Capstone: Integrate NanoSoC19
    • Capstone Brief
    • Stage 1: Memory Map and Interconnect
    • Stage 2: Clocks, Resets, Power
      • Clock Plan and Crossing Inventory
      • Reset Tree and First-Fetch Evidence
      • Power Domains and Power-Up Evidence
    • Stage 3: Interrupts and Boot
    • Stage 4: Verification and Signoff
    • Solutions
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←Stage 2: Clocks, Resets, Power
  1. Topics
  2. SoC Design
  3. Capstone: Integrate NanoSoC
  4. Stage 2: Clocks, Resets, Power
  5. Power Domains and Power-Up Evidence
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    Part 14 of 14, lesson 8 of 19Part 14 of 14/Capstone: Integrate NanoSoC/Lesson 8 of 19All levels

    Power Domains and Power-Up Evidence

    Produce a power-boundary signal list and bus-access traces.

    The observation to investigate

    Analyse the sleep-entry observations and the bus-completion observations separately before proposing causes for symptoms 6 and 10.

    Required behaviour

    Four groups feed live receivers; their counts sum to 114; the control for the clamps must stay powered when PD_SW is off.
    Capstone isolation census across the switchable boundary

    What to notice. Four groups feed live receivers; their counts sum to 114; the control for the clamps must stay powered when PD_SW is off.

    Check yourself How does the diagram account for 114 clamps?

    47 APB signals plus 52 SRAM0 signals plus 13 ROM signals plus two interrupt signals.

    Your investigation

    List every crossing signal and entry/exit dependency. Record how each bus access completes in each state. Propose faults that explain symptoms 6 and 10, build a rejecting check for each and capture corrected behaviour before reading Solutions.

    Inputs to start from

    • The two power domains (PD_SW and PD_AON) and the blocks in each, from The NanoSoC Tour.

    • The signal groups that leave the switchable domain: APB, SRAM0, ROM and interrupts.

    • The CLK_EN register and the sleep entry and wake sequence.

    • Symptoms 6 and 10 in the symptom table.

    Deliverable and pass criterion

    Deliverable. A list of every signal that crosses from the switchable domain into the always-on domain, grouped, with its count and safe value; and a bus-access trace for each state the control registers can select.

    Pass criterion. The group counts sum to the documented total, every crossing signal has a safe value and a control that stays powered, and each bus access completes or is refused in every state you traced.

    Evidence to hand in

    • The crossing list with counts and the arithmetic that sums them.

    • The sleep-entry observation and the bus-completion observation for symptoms 6 and 10, kept separate.

    • A check that fails when one group is missing from your list.

    Keep your diagnosis in your own report. After the stage checks, compare it with Solutions and run the provided injection checks.

    Related topics

    • Next: Stage 3: Interrupts and Boot

    • NanoSoC reference tour

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    See also

    • Clock Plan and Crossing Inventory