Every other section of this course builds something: a map, a fabric, a clock tree, a boot flow. This section decides whether all of it may leave the building. Signoff is not a second implementation pass; it is the governance view over the whole chip, owned by the integrator, that answers one question with evidence: what did we check, what did we excuse, and what risk remains. On NanoSoC that view fits on one manifest: the RTL revision, the map version, the constraint set, the implementation databases the results ran on, the check lists with their results, the waivers with their owners, and the dashboard that says how many metrics are red. Get this section right and tapeout is a calm meeting; get it wrong and it is an argument about a waiver nobody remembers approving.
Two dates are used in every topic, so they are named once here. The design freeze is the day the RTL, address map, constraints, power intent and firmware are stable: after it only reviewed fixes enter, and each one is logged as a post-freeze change that passes the three gates of the ECO topic. The signoff-complete date (the tapeout date) is the day every open violation is closed or waived, the implementation databases are frozen as the tapeout candidate, and the review decides go or no-go. NanoSoC teaching values, all illustrative: design freeze on day 130, today is day 150 (week 22), signoff-complete on day 182 (week 26). Fixes that land between the two dates are the burn-down the dashboard topic measures.
Topic | What it covers | After it you can... |
|---|---|---|
Versions, the tool-independent check list, freezing a baseline, a manifest checker | Assemble a manifest for NanoSoC and prove it complete with a script. | |
What may be waived, who approves, expiry and ageing, escape rate | Write a waiver that cannot age silently, and price a waiver that escapes. | |
Metrics across every discipline, reading a dashboard honestly, trends | Read a NanoSoC dashboard, spot a dishonest green, and call the trend. | |
The review meeting, evidence per owner, go and no-go rules, last-week surprises | Run the review, score go against no-go, and survive the last week. | |
Metal-only against full-respin thinking, late ECO discipline, spare cells | Cost an ECO against a respin and say what the spare cells buy. | |
From found bug to erratum, software workarounds, the loop back to the next chip | Record a NanoSoC erratum and write a workaround a driver can trust. |
Suggested order: top to bottom. The manifest comes first because everything else hangs off it: waivers are entries in it, the dashboard summarises it, the review audits it, ECOs amend it and errata extend it after tapeout. Readers facing a review next week can start at the fourth topic and follow the links back to the evidence each owner owes. The mechanism behind each discipline's checks lives in its owner course: implementation tapeout in Signoff and Tapeout, timing in Multi-Corner Multi-Mode Signoff, crossing discipline in CDC Signoff Methodology, verification in Sign-Off. This section teaches only the chip-level governance that ties them together.
Where the mechanism lives, so this section re-teaches none of it: the waiver policy for physical verification is PV Waiver Policy, the foundry handoff and revision tagging are Handoff to the Foundry, and the timing signoff worked end to end is Capstone: Timing Signoff Lab. Take from each only what the chip-level view needs: who owns the evidence, what revision it names and how a waiver is governed.
Only the integrator sees the whole chip: cross-boundary checks, waivers in one block that risk another, and the single baseline everything was verified against. Block signoff is an input; chip signoff is the decision.