Course map
- 1 lesson
Starts with How to Use This Course
- 1 lesson
Starts with The NanoSoC Tour
- 1 lesson
Starts with Reading Path
- 10 lessons
Starts with Glossary: Address and decode
- 1 lesson
Starts with SoC Metrics Reference
- 1 lesson
Starts with SoC Cheatsheet
- 12 lessons
Starts with What the Integrator Owns
- 21 lessons
Starts with Flat Versus Hierarchical
- 26 lessons
Starts with What an Address Map Is
- 26 lessons
Starts with Shared Bus, Crossbar and Hierarchy
- 24 lessons
Starts with Crystal, PLL and Dividers
- 21 lessons
Starts with Always On Versus Switchable
- 15 lessons
Starts with Levels, Polarity and Synchronisation
- 21 lessons
Starts with Macro Choice and Wrappers
- 21 lessons
Starts with What an IP Delivery Contains
- 21 lessons
Starts with Levels and What Only the Chip Can Show
- 18 lessons
Starts with Pad Types: Digital, Analog and Supply
- 18 lessons
Starts with What Goes in the Manifest
- 16 lessons
Starts with The Four-Part Answer
- 19 lessons
Starts with Requirements, Deliverables and Data
About this course
Choose a learning path
This course teaches SoC integration as it is practised: turning a specification and a set of blocks into one chip that boots, streams, sleeps and tapes out. The running example is NanoSoC, a small 32-bit system with a CPU, an AXI4 fabric, on-chip memories, a streaming DMA with its bridge, slow peripherals, and its own clock, reset and power controllers. Every section uses it, so the address map you decode in one section is the map the boot code jumps through in another and the power controller isolates in a third. Most sections contain worked numbers, and several have a short Python program that asserts them, so you can change a value and watch the consequence. It assumes you can read RTL, know what a flop and a clock are, and have met setup, hold and CDC in earlier courses; the owner courses are linked wherever their mechanics are needed.
Who it is for
Block owners becoming integrators: engineers with three to fifteen years of experience who own one block today and are about to own the wiring, the tables and the sequences between blocks.
Integrators and signoff leads who assemble subsystems and chips, run the top-level checks, and decide when a design is ready for the next milestone.
Architects who partition systems, set budgets and need the integration view of what their decisions cost downstream.
Anyone preparing for a senior interview who must answer whiteboard questions on maps, fabrics, clocks, resets, power, boot and signoff with numbers.
Three paths through the course
Block owner becoming integrator. Read How to Use This Course, then The NanoSoC Tour, then the sections in order from What SoC Integration Is through Architecture and Budgets, Memory Maps and Address Decode, Interconnect and Bus Fabrics, Clock and Reset Architecture, Power Architecture, Interrupts, DMA and Peripherals and Memories, Boot and Security, followed by IP Integration and Handoff, Top-Level Verification and Bring-up, Package, Pads and I/O and Chip Signoff and Tapeout. Finish with the Capstone, which integrates NanoSoC end to end. This path is the whole course, about 45 hours.
Integrator and signoff lead. Take the tour, then the contracts and budget-governance topics of the flow and architecture sections, the full map, fabric, clock, reset and power sections, and everything from IP handoff to signoff: the handoff gate, the verification plan, the package interface, the waiver board and the readiness review. It assumes you already know block implementation; take the block-owner path first if you do not.
Interview in two weeks. Take the tour, read How to Use This Course for the study routine, then work Interview Prep: the whiteboard framework, the design scenarios, the rapid-fire rounds and the numeric drills. Attempt every drill on paper before you read its answer, and add the topic hubs of sections 5 to 8 (clock and reset, power, interrupts and DMA, memories and boot) for the numbers you will be asked about.
What you can do after the course
Build a memory map with aligned power-of-two windows, and check it for overlaps, aliases and holes with a script.
Size an interconnect against bandwidth and latency budgets, and say which master loses when a slave is shared.
Design clock, reset and power-up sequences with release order, and name what each step waits for.
Route interrupts from source to CPU with a wiring table, and bound the worst-case latency.
Integrate a streaming DMA behind its stream bridge: program both, move data end to end, and handle their errors.
Plan a boot flow from reset vector to first application word, and say where the time goes.
Hand IP over cleanly: demand the collateral, run the acceptance gate, and refuse an incomplete bundle.
Plan top-level verification and bring-up: connectivity, boot, interrupts, DMA, power states and performance.
Run signoff and waivers: read the closure dashboards, age a waiver, and call a tapeout review.
Answer a whiteboard question as Assumption, Mechanism, Trade-off, Evidence, with a drawing and a number.
Section map
Section | One line |
|---|---|
Roles, handoffs, milestones, contracts, and reading a specification as budgets. | |
Partitions, area, timing, power and bandwidth budgets, margin burn-down, and the multi-die view. | |
Map design, decode, default slaves, register banks, security regions, and map verification. | |
Topologies, AXI integration detail, ordering and deadlock, QoS, firewalls, and budget checks. | |
Sources and PLLs, gating, domains, crossings, always-on wake policy, reset trees, sequencing and release. | |
Domains and states, isolation and retention, the sequencer, cold start, supplies, and DVFS. | |
Controller integration, routing and latency, the NanoSoC DMA, the peripheral subsystem, and pad muxing. | |
Memory wrappers, error handling, boot ROM and modes, fuses, secure boot, and the security partition. | |
Collateral and versioning, wrappers, integration lint, constraints, test, debug, and safety. | |
Chip verification strategy, connectivity, firmware co-simulation, performance, emulation, and readiness. | |
IO cells, pad counts, ballout, power delivery, ESD, and test and debug pins. | |
The signoff manifest, waivers, dashboards, the readiness review, ECOs, and errata. | |
The whiteboard framework, design scenarios, storms, rapid-fire rounds, and numeric drills. | |
Integrate the whole chip on paper with a running checker: map, fabric, clocks, boot, and signoff. |
How to study
Read How to Use This Course, then the Reading Path for your role.
Keep The NanoSoC Tour open while you read: each lesson sits in one block of that chip.
Run the Python blocks and change a number. Which assertion fails first tells you which relationship matters.
Answer every check-yourself before revealing its answer.
Keep the Glossary, the Metrics Reference and the Cheatsheet beside you.
Finish with the capstone: it spends numbers from every earlier section.
Time and prerequisites
Allow about 45 hours to read, about 80 with the worked examples and exercises. These are planning estimates, not measurements of learners: see the Reading Path for how they are built. If RTL hierarchy, CDC crossings and timing constraints are new to you, start with the companions named in How to Use This Course before the fabric and clock sections. All numbers are NanoSoC teaching values unless the text says otherwise; no real process, library or product data is used.
Check yourself Which path suits an engineer who has never integrated a chip, and where does it end?
The block-owner path: it follows the chip in order from flow and budgets to signoff, and it ends with the capstone, which spends every section at once.