Use the first-fetch observation to decide what to measure. Capture when each receiver becomes ready.
What to notice. Fabric release precedes CPU release; the gap has a named clock; the first transaction fetches from ROM.
rst_sys_n release, the eight-system-cycle gap and the two-CPU-cycle synchroniser delay.
Compute release timestamps and annotate the observed fetch. Propose a fault that explains symptom 2 and design a trace that tells it apart from a slow ROM response. Document the corrected invariant before inspecting the worked checks.
The reset tree in The NanoSoC Tour: rst_per_n, rst_sys_n and rst_cpu_n, with the synchroniser depth of each.
The PLL lock wait, the clock-gate enables and the first ROM fetch address.
Symptom 2 in the symptom table.
Deliverable. A release timeline with one row per reset step (step, time in microseconds, cumulative time) and an annotated first-fetch trace.
Pass criterion. The timeline sums to the documented hardware reset time, each receiver is ready before the first transaction aimed at it, and the check fails on a timeline whose steps you reorder.
The timeline with the clock period used for each step.
The annotated trace for symptom 2: when the first fetch address leaves the CPU and when each receiver can accept it.
The reordered timeline your check rejects.
Keep your diagnosis in your own report. After the stage checks, compare it with Solutions and run the provided injection checks.