An integrator reduces a chip to a short list of numbers that can be checked: how fast data moves, how long an access takes, how full the die is, what each state costs, how long reset takes. This page defines each family, gives the formula, quotes the NanoSoC value and points to the lesson that derives it. All values are NanoSoC teaching values, not data for any real process or product, and no target is implied: acceptable limits are project decisions.
Metric | Definition and formula | NanoSoC value | Taught in |
|---|---|---|---|
Peak bandwidth | Width in bytes x clock frequency. A ceiling, never a forecast. | 4 B x 96 MHz = 384.0 MB/s on the fabric; 768.0 MB/s at the CPU port (192 MHz) | |
Burst efficiency | L / (L + 1) for L beats and one bubble cycle per burst. | 50.0%, 80.0%, 88.9%, 94.1% for L = 1, 4, 8, 16 | |
Sustained bandwidth | Peak x efficiency, and then the minimum over every link in the path. | 361.4 MB/s at burst 16 (384 x 16/17); 307.2 MB/s at burst 4 | |
Shared-bank sustained rate | A single-port memory serves reads and writes together, so each stream gets half. | 180.7 MB/s per stream when source and destination share one SRAM | |
Total memory bandwidth | Sum of the sustained rates of independent banks. | 2 x 361.4 = 722.8 MB/s across SRAM0 and SRAM1 | |
Register bus rate | Width x clock / clocks per access, with bridge cycles added for the sustained figure. | APB at clk_sys: 128.0 MB/s bus only, 76.8 MB/s with bridge; APB at clk_per: 48.0 MB/s bus only, 19.2 MB/s through the clock-crossing bridge | |
Serial line rate | Bit clock divided by the divisor, times the bits per byte. | UART 24e6 / (16 x 13) = 115,384.6 baud, 0.0115 MB/s; SPI 6 Mb/s = 0.750 MB/s | |
Link utilisation | Achieved rate divided by the sustained rate of that link; it identifies the link that limits the path. | No fixed value: the fabric links are equal at 361.4 MB/s, so the shared SRAM bank is the limiter in the shared-bank case |
Metric | Definition and formula | NanoSoC value | Taught in |
|---|---|---|---|
Clock periods | 1 / frequency. | T_cpu 5.2083 ns, T_sys 10.4167 ns, T_per 41.6667 ns; 1 T_sys = 2 T_cpu | |
CPU single read of SRAM or ROM | Sum of the stages in cycles of each clock the stage runs in: issue, crossing, fabric, memory, crossing back. | 18 T_cpu = 93.75 ns (42.67 MB/s) | |
Instruction line fill | First word latency plus one beat per T_sys for the rest. | 24 T_cpu = 125 ns for a 4-word line | |
CPU read of a clk_sys register | Crossing, fabric, bridge accept, APB access, bridge respond. | 24 T_cpu = 125 ns | |
CPU read of a clk_per register | As above plus the request and response synchronisation in the crossing bridge. | 281.25 ns (54 T_cpu) | |
DMA job time | N input beats plus pipeline fill and drain. | N + 8 T_sys; 64 words give 72 T_sys = 750 ns | |
Interrupt latency | Two flops in clk_per, one INTC output register, two flops in clk_cpu; the worst case adds one clk_per and one clk_cpu for alignment. | 135.4 ns best (3 T_per + 2 T_cpu), 182.3 ns worst; shortest pulse seen reliably 2 T_per = 83.3 ns |
Metric | Definition and formula | NanoSoC value | Taught in |
|---|---|---|---|
Block area subtotal | Sum of block areas. | 0.585 mm2 (PD_SW 0.372, PD_AON 0.213) | |
Core area | Blocks plus clock tree, routing and fill overhead. | 0.585 x 1.12 = 0.655 mm2 | |
Utilisation | Core area over the die core budget. State the denominator. | 0.655 / 0.940 = 69.7% | |
Memory share of area | Memory block area over block area subtotal. | (0.100 + 0.100 + 0.025 + 0.012) / 0.585 = 40.5% | |
Power per state | Dynamic plus leakage, per state. | RUN 82.74 mW; IDLE 16.89 mW; SLEEP 1.40 mW | |
Dynamic and leakage split | The two terms of the same total. | RUN 77.10 + 5.64; IDLE 11.25 + 5.64; SLEEP 0.16 + 1.24 mW | |
Largest consumer | Block power over total power. | CPU core 39.20 mW of 82.74 mW = 47.4% in RUN | |
Energy per job | Power x time. | 82.74 mW x 750 ns = 62.1 nJ for a 64-word DMA job | |
Isolation cell count | Signals leaving the switchable domain into the always-on one. | 47 + 52 + 13 + 2 = 114 clamps |
Metric | Definition and formula | NanoSoC value | Taught in |
|---|---|---|---|
PLL output | Reference x feedback multiply / reference divide. | 24 MHz x 32 / 1 = 768 MHz VCO | |
Clock ratios | Frequencies of the domains reduced to integers. | clk_cpu : clk_sys : clk_per = 192 : 96 : 24 = 8 : 4 : 1 | |
PLL lock time | Lock count x clk_per period. | 256 x 41.667 ns = 10.667 us | |
Crossing count | Crossing groups in the inventory. | 10 groups (X1 to X10) | |
Reset release times | Cycles at each step times that clock's period. | Oscillator ready 42.667 us; rst_per_n +83.333 ns; PLL ready +10.833 us; clocks open +83.333 ns; rst_sys_n +187.5 ns; rst_cpu_n +93.75 ns | |
Hardware boot time | Sum of the reset release steps. | 53.948 us | |
Minimum reset width | Cycles of the domain's own clock. | 16 cycles for software reset; pad reset must stay low more than 16 clk_per (666.7 ns) to pass the filter | |
Power-down time | Sum of the sequence steps in clk_per cycles. | 2 + 2 + 2 + 64 = 70 cycles = 2.917 us | |
Power-up (wake) time | Switch ramp, power-good, PLL relock, clocks, then release steps. | 14.073 us |
Metric | Definition and formula | NanoSoC value | Taught in |
|---|---|---|---|
Total boot time | Sum of hardware steps and ROM steps, one access at a time. | 12.581 ms to the jump to 0x2000_0000 | |
Boot time shares | Step time over total. | SPI image load 10,928.000 us = 86.9%; banner at 115,384.6 baud 1,386.667 us = 11.0%; everything else 2.1%; hardware reset 0.43% | |
Mapped end and slot count | Last address with a slave, and mapped slots. | Mapped space ends at 0x4000_6FFF; 7 peripheral slots of 4 KB; 2 SRAMs of 64 KB; ROM 16 KB | |
Overlap and alignment check | For sorted regions, base + size must not exceed the next base; each base must be a multiple of its size. | 0 overlaps, 0 misaligned bases in the map; the deliberate DMA alias is 16 images of 256 bytes | |
Hole response | Which response each hole returns. | H1, H2 and H4 give DECERR within 2 clk_sys cycles per beat; H3 gives SLVERR | |
Waiver ageing | Age = today minus grant date; review-by and expiry per class. | Teaching rule: false violations review at 30 days and expire at 90; proven-safe and bounded-risk review at 90 and expire at 180; an ECO on the path expires the waiver at once | |
Escape rate | Waivers that caused a silicon issue over waivers granted. | Teaching example: 2 of 93 = 2.2%, with a containment bill of 15 engineer-weeks | |
Coverage | Top-level plan items exercised by must-pass tests on the frozen baseline. | No fixed percentage: the dashboard needs the boot, interrupt, DMA and power-state tests passing; the manifest carries at least six result rows |
The block below recomputes a sample from each family from its inputs and asserts the result. Change a frequency, a width or a cycle count and the first affected assertion fails, which shows which relationships tie the numbers together.
# NanoSoC teaching values: recompute the quoted metrics from their inputs
W = 4 # bytes per beat
f_cpu, f_sys, f_per = 192.0, 96.0, 24.0 # MHz
t_cpu, t_sys, t_per = 1000 / f_cpu, 1000 / f_sys, 1000 / f_per # ns
assert f_cpu / f_per == 8 and f_sys / f_per == 4
assert (round(t_cpu, 4), round(t_sys, 4), round(t_per, 4)) == (5.2083, 10.4167, 41.6667)
assert 24 * 32 // 1 == 768 and 768 // 4 == 192 and 768 // 8 == 96
# bandwidth
peak = W * f_sys
assert peak == 384.0
eff = lambda n: n / (n + 1)
sust = {n: peak * eff(n) for n in (1, 4, 8, 16)}
assert [round(sust[n], 1) for n in (1, 4, 8, 16)] == [192.0, 307.2, 341.3, 361.4]
assert round(sust[16] / 2, 1) == 180.7 and round(2 * sust[16], 1) == 722.8
assert W * f_sys / 3 == 128.0 and W * f_sys / 5 == 76.8 and W * f_per / 2 == 48.0
assert round(W / (208.33e-9) / 1e6, 1) == 19.2 # 4 bytes per 208.33 ns
# latency
assert round(18 * t_cpu, 2) == 93.75 and round(24 * t_cpu, 2) == 125.0
assert round(9 * t_sys + 4 * t_per + 4 * t_cpu, 2) == 281.25
assert round((64 + 8) * t_sys, 1) == 750.0
best = 3 * t_per + 2 * t_cpu
worst = best + t_per + t_cpu
assert round(best, 1) == 135.4 and round(worst, 1) == 182.3
# reset and boot
hw_us = ((1024 + 2 + 260 + 2) * t_per + (18 + 8) * t_sys + 2 * t_cpu) / 1000
assert round(hw_us, 3) == 53.948
spi_us = (8192 + 4) * 8 / 6.0 # bits / (Mb/s) = us
banner_us = 160 / (24e6 / (16 * 13)) * 1e6
assert round(spi_us, 1) == 10928.0 and round(banner_us, 1) == 1386.7
total_us = 12580.917
shares = (spi_us / total_us, banner_us / total_us, hw_us / total_us)
assert [round(100 * s, 1) for s in shares[:2]] == [86.9, 11.0] and round(100 * shares[2], 2) == 0.43
# area and power
blocks = 0.372 + 0.213
core = blocks * 1.12
assert round(blocks, 3) == 0.585 and round(core, 3) == 0.655
assert round(0.655 / 0.940 * 100, 1) == 69.7
assert round((0.100 + 0.100 + 0.025 + 0.012) / 0.585 * 100, 1) == 40.5
run, idle, sleep = 77.10 + 5.64, 11.25 + 5.64, 0.16 + 1.24
assert (round(run, 2), round(idle, 2), round(sleep, 2)) == (82.74, 16.89, 1.40)
assert round((38.00 + 1.20) / run * 100, 1) == 47.4
assert round(run * 750 / 1000, 1) == 62.1 # mW x ns / 1000 = nJ
assert 47 + 52 + 13 + 2 == 114
print("PASS: metric families recompute from their inputs")Read the scope first: which link, domain or state, which baseline and which date.
Read the definition: peak or sustained, best or worst case, with or without the bridge.
Read the denominator for every percentage: utilisation over the core or the die budget; a share over the total of that run.
Compare with the budget and with the previous run on the same baseline.
Only then react to the headline number.
The memory bank. A single-port SRAM serves reads and writes together, so a source and a destination in the same bank each get half of 361.4 MB/s. Moving the destination to the other bank restores the full rate.