The die ends at the pads, but the chip does not end at the die: every signal leaves through a pad cell, a bump or wire, a package trace and a ball before the board ever sees it, and every ampere of supply current comes back the same way. The integrator owns that boundary end to end. On NanoSoC the boundary is small enough to hold in one hand — 19 signal pads and 12 supply pads, 31 in total, as NanoSoC teaching values — yet it already asks every question this section teaches: which pads drive and which only listen, how many supply pairs keep switching noise inside its budget, which ball carries what, how the 0.9 V rail survives the journey from board to transistor, where the discharge paths sit, and which pins must behave safely before software runs. The UART and the SPI share the sixteen GPIO pads rather than owning pads of their own, and NanoSoC has no JTAG, test-mode or boot-mode pins: it boots over SPI. The last topic of the section prices those missing pins as a clearly labelled extension. This section teaches the integrator's view throughout: the physical implementation of rings, bumps and protection belongs to the physical design course, and each lesson says so and links there.
Topic | What it covers | After it you can... |
|---|---|---|
Digital, analog and supply pads; the ring; function, drive and pull options | Choose the pad type for every NanoSoC signal and state its reset behaviour. | |
Signal versus supply pad ratios, SSN estimation as a calculator input, pairing and drive choices | Budget the NanoSoC pad count and prove the switching-noise allowance closes. | |
Package types, ball assignment rules, pinout review with the board team, escape routing | Assign every NanoSoC pad to a ball and pass a pinout review. | |
Supply paths, bump and via resistance arithmetic, decoupling hierarchy, on-chip link | Compute the NanoSoC rail drop from board to transistor and place each decap where it works. | |
What the integrator checks, cross-domain discharge paths, pad-to-core interfaces | Check the NanoSoC discharge paths and name what the protection review must show. | |
An optional test and boot port that NanoSoC v1 does not have: dedicated versus shared pins, straps, JTAG, safe defaults | Price seven extra pins in pads and balls, sample straps safely, and audit every pin's reset default. |
Suggested order: top to bottom. Pads first, because the package and the power delivery both consume the pad list; then the count and noise budget, because they change how many supply pads the ballout gets; then the package itself, then the supply path through it, then protection, then, as an extension, the pins NanoSoC could add for test and debug and what they would cost. Readers chasing a specific failure — contention at reset, a noisy interface, a rail that droops — can start at the first, second or fourth topic and follow the links back. For the physical implementation of rings and bumps see Bump Map and Package Interface and ESD and IO Ring Integration; for on-chip grid drop see Power Grid IR Drop.
Because the decisions cross both sides: pad drive and supply pairing set the noise the board sees, ball assignment sets the escape the board can route, and the reset state of every pin is a contract with software. One owner must hold the pin list, the ballout and the reset-state table together.