Every block on NanoSoC arrived from somewhere: the DMA from the verification course's bench, the SRAMs from a memory compiler, the interconnect from a generator, the peripherals from earlier projects. Integration is the discipline of receiving those blocks without trusting them: demanding the full collateral, wrapping them so their quirks stop at the boundary, proving every connection with a table and a checker, merging their constraints at the top, and wiring test, debug and safety around them. This section teaches that working-integrator view. Its tools are checklists, tables and review gates rather than waveforms, and every lesson ends with what the review asks for and the failure story that justifies it.
Topic | What it covers | After it you can... |
|---|---|---|
The full delivery list, versioning and change notices, the acceptance gate | Demand a complete delivery, judge a version bump, and run the acceptance check. | |
Why blocks are wrapped, width and protocol adapters, the NanoSoC wrappers | Wrap a block so its quirks stop at the boundary and prove the adapter correct. | |
Structural checks, connectivity tables, a Python checker, tie-offs | Own the connectivity table and catch a width or tie-off bug before simulation. | |
Merging block constraints, top clock definitions, exception review | Merge block constraints into one top-level file and defend every exception. | |
Test-mode architecture, wrapper cells, scan clock and reset muxing, test pins | Plan scan integration across the chip and sequence test-mode entry safely. | |
Debug access and TAP chaining, trace, secured debug, debug power | Chain the debug path, budget trace, and lock debug without breaking bring-up. | |
Safety goals, fault detection and reaction, lockstep and parity, fault reporting | Turn a safety goal into detection, reaction and reporting wiring. |
Suggested order: top to bottom. Collateral first, because everything later consumes the delivery; then wrappers, which define the boundary the checks verify; then lint and connectivity, the daily working tools. Constraint merge follows, because it needs the wrapper boundaries and the clock plan to be settled. DFT and debug come next as the two access architectures overlaid on the same chip, and safety closes the section because its fault wiring touches all of them. Readers chasing one failure can start at its topic directly: each topic overview lists what its lessons let you do.
Because every block arrives with assumptions its author never wrote down: widths, resets, sidebands, constraints. The integrator's job is to surface those assumptions at the boundary with wrappers and checkers, not to discover them in silicon.