Every number the chip promises about speed lives in the fabric: 384 MB/s peak per 32-bit link, 361.4 sustained with long bursts, 93.75 ns for a CPU word from SRAM, 281.25 ns for a slow peripheral register. The interconnect is where those numbers are made or lost, and where the failures hide that only appear with all masters running at once: a burst crossing a 4 KB page, an ID bit dropped in a bridge, a dependency ring through a shared slave, a bulk stream starving a fill. This section treats the fabric as a chip-level IP with a configuration, a topology, a QoS plan and a sign-off, all worked on the NanoSoC 2-master by 4-slave crossbar and its APB tree.
Topic | What it covers | After it you can... |
|---|---|---|
Shared bus, crossbar and hierarchy; the axi2apb bridge and apb_cdc with their costs; register slices | Choose a topology, trace a bridge access, budget every crossing and place a register slice. | |
IDs, outstanding counts, the 4 KB rule, width and clock conversion | Size IDs, split bursts at page edges, and cross clock domains. | |
Ordering guarantees, SoC-level deadlock, prevention and debug | State the ordering contract and break or debug a dependency cycle. | |
Round-robin cost, starvation, what really bounds a wait, QoS on NanoSoC | Bound worst waits and say which QoS features NanoSoC has and which are proposals. | |
Packets versus crossbars, message classes, the address-to-node map, island crossings, the NanoSoC verdict | Price a NoC against a crossbar and check the integration surface of one. | |
Snoop traffic, I/O coherence for DMA, migration from non-coherent NanoSoC (illustrative numbers) | Cost coherence as fabric, map, verification and software delta. | |
AxPROT filters and denied bursts, a complete policy table, a proposed master-ID firewall, denial debug | Enforce per-region policy and diagnose any denied access. | |
The link table as arithmetic, latency checks, counters and misses | Prove the chip meets its bandwidth and latency budgets. |
Suggested order: top to bottom. Topology first, because everything else hangs off it; AXI detail and ordering next, because they constrain every bridge; QoS then NoC, because the NoC replays the arbitration argument at scale; coherence and firewalls, which add traffic and policy to the same wires; verification last, which checks the whole section. Readers chasing one failure can start at its topic and follow the links back. For signal-level protocol meaning see AXI4; for the generic bus view see Bus Integration. NanoSoC itself has a round-robin crossbar with an AxPROT filter and nothing more: where a lesson discusses priority, rate regulators, a master-ID firewall or a NoC, it says whether that is built or proposed.
Topologies and bridges first: the usual cause is the SBR's source and destination sharing one SRAM bank, which halves both directions to 180.7 MB/s. Bandwidth and latency verification confirms it with counters. QoS and arbitration is next if a CPU is competing with the SBR. Firewalls only enter if errors accompany the slowdown.