Skip to content
DenseChip
Learn
PracticeCode labInterview

DenseChip

Navigate

Menu

LearnPracticeCode labInterview

Tools

All toolsSV editorCode repoResume
DenseChip

Practice, courses, and chip-design tools in one focused workspace.

LearnPracticeCode labInterviewToolsLearning paths

© 2026 DenseChip

AboutRoadmapCareersInternshipsFAQContactPrivacyTerms
Skip to lesson

Course contents

  • How to Use This Course
  • The NanoSoC Tour
  • Reading Path
  • SoC Glossary10
  • SoC Metrics Reference
  • SoC Cheatsheet
  • What SoC Integration Is12
  • Architecture and Budgets21
  • Memory Maps and Address Decode26
  • Interconnect and Bus Fabrics26
  • Clock and Reset Architecture24
  • Power Architecture21
  • Interrupts, DMA and Peripherals15
  • Memories, Boot and Security21
  • IP Integration and Handoff21
  • Top-Level Verification and Bring-up21
  • Package, Pads and I/O18
  • Chip Signoff and Tapeout18
  • SoC Interview Prep16
  • Capstone: Integrate NanoSoC19
    • Capstone Brief
    • Stage 1: Memory Map and Interconnect
      • Map Table and Decoder Probes
      • Decode and Response Codes
      • Link Table and Throughput Evidence
    • Stage 2: Clocks, Resets, Power
    • Stage 3: Interrupts and Boot
    • Stage 4: Verification and Signoff
    • Solutions
Loading lesson

←Stage 1: Memory Map and Interconnect
  1. Topics
  2. SoC Design
  3. Capstone: Integrate NanoSoC
  4. Stage 1: Memory Map and Interconnect
  5. Link Table and Throughput Evidence
On this page

    Part 14 of 14, lesson 5 of 19Part 14 of 14/Capstone: Integrate NanoSoC/Lesson 5 of 19All levels

    Link Table and Throughput Evidence

    Produce a link table with peak, sustained and shared-bank rates.

    The observation to investigate

    Functional success does not establish the throughput contract. Compare the observed transfer time with the time your link table predicts.

    Required behaviour

    Fabric directions are separate; each SRAM port serves reads and writes together; placement changes resource demand.
    Capstone separate-bank and shared-bank throughput

    What to notice. Fabric directions are separate; each SRAM port serves reads and writes together; placement changes resource demand.

    Check yourself Which placement permits 361.4 MB/s in each direction?

    Separate SRAM banks, one serving reads and one serving writes.

    Your investigation

    Recompute peak and sustained rates from 32 bits, 96 MHz and L/(L+1). Compare two-bank and one-bank placement, then price a 64-word job including eight fill-and-drain cycles. Write a failing placement check before consulting the worked example.

    Inputs to start from

    • The link table in Link Table and Sustained Rates.

    • The fabric: 32 bits wide at 96 MHz, bursts of 16 beats, one bubble per burst; two SRAM banks with one port each.

    • A 64-word job with eight fill-and-drain cycles.

    Deliverable and pass criterion

    Deliverable. A link table with peak, sustained and shared-bank rate for each link, and a cycle count for the 64-word job under two-bank and one-bank placement.

    Pass criterion. Peak, sustained and shared-bank rates recompute from the three inputs above, the job time follows from them, and a placement check fails when source and destination share a bank.

    Evidence to hand in

    • Each rate with its formula and units.

    • The 64-word job time for both placements, with the fill-and-drain cycles shown separately.

    • The failing placement check and the line of output that shows it failing.

    Keep your diagnosis in your own report. After the stage checks, compare it with Solutions and run the provided injection checks.

    Related topics

    • Next: Stage 2: Clocks, Resets, Power

    • NanoSoC reference tour

    Previous

    270 / 294

    Next: Stage 2: Clocks, Resets, Power

    Up next

    Up nextStage 2: Clocks, Resets, Power

    Sign in to save progress

    Practice this lessonPrevious lessonReport an error

    See also

    • Map Table and Decoder Probes