Skip to content
DenseChip
Learn
PracticeCode labInterview

DenseChip

Navigate

Menu

LearnPracticeCode labInterview

Tools

All toolsSV editorCode repoResume
DenseChip

Practice, courses, and chip-design tools in one focused workspace.

LearnPracticeCode labInterviewToolsLearning paths

© 2026 DenseChip

AboutRoadmapCareersInternshipsFAQContactPrivacyTerms
Skip to lesson

Course contents

  • How to Use This Course
  • The NanoSoC Tour
  • Reading Path
  • SoC Glossary10
  • SoC Metrics Reference
  • SoC Cheatsheet
  • What SoC Integration Is12
  • Architecture and Budgets21
  • Memory Maps and Address Decode26
  • Interconnect and Bus Fabrics26
  • Clock and Reset Architecture24
  • Power Architecture21
  • Interrupts, DMA and Peripherals15
  • Memories, Boot and Security21
  • IP Integration and Handoff21
  • Top-Level Verification and Bring-up21
  • Package, Pads and I/O18
  • Chip Signoff and Tapeout18
  • SoC Interview Prep16
  • Capstone: Integrate NanoSoC19
    • Capstone Brief
    • Stage 1: Memory Map and Interconnect
      • Map Table and Decoder Probes
      • Decode and Response Codes
      • Link Table and Throughput Evidence
    • Stage 2: Clocks, Resets, Power
    • Stage 3: Interrupts and Boot
    • Stage 4: Verification and Signoff
    • Solutions
Loading lesson

←Stage 1: Memory Map and Interconnect
  1. Topics
  2. SoC Design
  3. Capstone: Integrate NanoSoC
  4. Stage 1: Memory Map and Interconnect
  5. Decode and Response Codes
On this page

    Part 14 of 14, lesson 4 of 19Part 14 of 14/Capstone: Integrate NanoSoC/Lesson 4 of 19All levels

    Decode and Response Codes

    Produce a response predictor and a register table independent of the observed wiring.

    The observation to investigate

    A successful CTRL read alone does not establish that all DMA registers are reachable. Compare each expected register and response with the observations in symptom 4.

    Required behaviour

    H3 is inside APB; other holes reach the fabric default; the DMA slot has a fixed set of register offsets.
    Capstone hole responders and DMA addressing requirements

    What to notice. H3 is inside APB; other holes reach the fabric default; the DMA slot has a fixed set of register offsets.

    Check yourself Follow H3 through the diagram: what response reaches the CPU?

    AXI SLVERR, translated from the APB default slave PSLVERR.

    Your investigation

    Create a response predictor for every unmapped range and a register predictor for every documented DMA offset. Find and inject a fault that reproduces symptom 4, then check every documented register after your correction.

    Inputs to start from

    • The five DMA register offsets (CTRL, STATUS, LEN, KEY, COUNT) from Programming the DMA Registers.

    • The four unmapped ranges (H1 to H4) and their response codes in The NanoSoC Tour.

    • Symptom 4 in the symptom table.

    Deliverable and pass criterion

    Deliverable. A response table with one probe per unmapped range and the expected response code, and a register table that maps each documented DMA offset to the register you expect to read.

    Pass criterion. Your predictor agrees with the documented response for every probe and with the documented register for every offset; changing any single offset in your table makes the check fail.

    Evidence to hand in

    • The response table: probe address, expected code, and the block that must produce it.

    • The register table: offset, expected register, observed register for symptom 4.

    • Which repeated offsets you consider intended, and where the documentation says so.

    Keep your diagnosis in your own report. After the stage checks, compare it with Solutions and run the provided injection checks.

    Related topics

    • Next: Link Table and Throughput Evidence

    • NanoSoC reference tour

    Previous

    269 / 294

    Next: Link Table and Throughput Evidence

    Up next

    Up nextLink Table and Throughput Evidence

    Sign in to save progress

    Practice this lessonPrevious lessonReport an error