For symptom 3, compare source, controller and CPU observations. Derive the expected map independently of the implementation.
What to notice. Every source has a distinct input; priority follows input number; the CPU receives one level.
DMA input 1, which outranks UART input 3.
Force one source at a time and record RAW, ENABLE, PENDING and TOP against an independent expected map. Compute the latency through both synchronisers and the output register. Find and inject a fault reproducing symptom 3 and show which observation rejects it.
The interrupt table in The NanoSoC Tour: inputs 0 to 7, with 6 and 7 reserved.
The controller registers RAW, ENABLE, PENDING and TOP, and the rule that the lowest input number wins.
Symptom 3 in the symptom table, and the delays through the two synchronisers and the output register.
Deliverable. An expected map (source to input number) with a per-source test log of RAW, ENABLE, PENDING and TOP, and a best-case and worst-case latency budget.
Pass criterion. Forcing each source sets exactly its expected RAW bit and no other, TOP follows priority when two sources are pending, and the latency equals the sum of the stage delays you derived.
The expected map and the six test-log rows.
For symptom 3, the RAW bits you read against the ones you expected.
The latency table with each stage's delay in nanoseconds.
Keep your diagnosis in your own report. After the stage checks, compare it with Solutions and run the provided injection checks.