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Course contents

  • How to Use This Course
  • The NanoSoC Tour
  • Reading Path
  • SoC Glossary10
  • SoC Metrics Reference
  • SoC Cheatsheet
  • What SoC Integration Is12
  • Architecture and Budgets21
  • Memory Maps and Address Decode26
  • Interconnect and Bus Fabrics26
  • Clock and Reset Architecture24
  • Power Architecture21
  • Interrupts, DMA and Peripherals15
  • Memories, Boot and Security21
  • IP Integration and Handoff21
  • Top-Level Verification and Bring-up21
  • Package, Pads and I/O18
  • Chip Signoff and Tapeout18
  • SoC Interview Prep16
  • Capstone: Integrate NanoSoC19
    • Capstone Brief
    • Stage 1: Memory Map and Interconnect
    • Stage 2: Clocks, Resets, Power
    • Stage 3: Interrupts and Boot
      • Interrupt Map and Latency Budget
      • DMA Programming Sequence and Driver Trace
      • Boot Flow and Secure Partition
    • Stage 4: Verification and Signoff
    • Solutions
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←Stage 3: Interrupts and Boot
  1. Topics
  2. SoC Design
  3. Capstone: Integrate NanoSoC
  4. Stage 3: Interrupts and Boot
  5. Boot Flow and Secure Partition
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    Part 14 of 14, lesson 11 of 19Part 14 of 14/Capstone: Integrate NanoSoC/Lesson 11 of 19All levels

    Boot Flow and Secure Partition

    Produce a sixteen-step boot record and a security matrix.

    The observation to investigate

    A boot-time sum does not prove that wake preserves the image or that every initiator obeys the access policy. Record both contracts separately.

    Required behaviour

    The cause read comes first; wake preserves SRAM0; both paths hand control to 0x2000_0000.
    Capstone cold-boot and retained-image handoff requirements

    What to notice. The cause read comes first; wake preserves SRAM0; both paths hand control to 0x2000_0000.

    Check yourself Why must the WAKE branch avoid the cold-boot clear?

    It resumes the retained SRAM0 image; clearing that memory would destroy the image to resume.

    Your investigation

    Add all sixteen boot steps with duration and cumulative time. Write a security matrix for each master and destination, then demonstrate any route that remains open. State what a model PASS establishes and what further evidence a closed partition would require.

    Inputs to start from

    • The sixteen boot steps and their durations in The NanoSoC Boot Flow in Time.

    • The reset-cause register and the retained SRAM0 image used by the wake path.

    • The secure column of the address map and the three bus masters (CPU, SBR, DMA stream path).

    Deliverable and pass criterion

    Deliverable. A boot record of sixteen rows (step, duration, cumulative time) and a security matrix of master by destination region, with the access attribute each master presents.

    Pass criterion. The record sums to the documented boot total, the wake path never clears SRAM0, every matrix cell is allowed or refused for a stated reason, and your readiness note says what a model PASS does and does not establish.

    Evidence to hand in

    • The boot record with the sum and the largest single share.

    • The matrix, with any cell where the outcome depends on software behaviour marked.

    • What further evidence a closed secure partition would need.

    Keep your diagnosis in your own report. After the stage checks, compare it with Solutions and run the provided injection checks.

    Related topics

    • Next: Stage 4: Verification and Signoff

    • NanoSoC reference tour

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    See also

    • Interrupt Map and Latency Budget