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Course contents

  • How to Use This Course
  • The NanoSoC Tour
  • Reading Path
  • SoC Glossary10
  • SoC Metrics Reference
  • SoC Cheatsheet
  • What SoC Integration Is12
  • Architecture and Budgets21
  • Memory Maps and Address Decode26
  • Interconnect and Bus Fabrics26
  • Clock and Reset Architecture24
  • Power Architecture21
  • Interrupts, DMA and Peripherals15
  • Memories, Boot and Security21
  • IP Integration and Handoff21
  • Top-Level Verification and Bring-up21
  • Package, Pads and I/O18
  • Chip Signoff and Tapeout18
  • SoC Interview Prep16
  • Capstone: Integrate NanoSoC19
    • Capstone Brief
    • Stage 1: Memory Map and Interconnect
    • Stage 2: Clocks, Resets, Power
    • Stage 3: Interrupts and Boot
      • Interrupt Map and Latency Budget
      • DMA Programming Sequence and Driver Trace
      • Boot Flow and Secure Partition
    • Stage 4: Verification and Signoff
    • Solutions
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←Stage 3: Interrupts and Boot
  1. Topics
  2. SoC Design
  3. Capstone: Integrate NanoSoC
  4. Stage 3: Interrupts and Boot
  5. DMA Programming Sequence and Driver Trace
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    Part 14 of 14, lesson 10 of 19Part 14 of 14/Capstone: Integrate NanoSoC/Lesson 10 of 19All levels

    DMA Programming Sequence and Driver Trace

    Produce a driver trace and one hypothesis row per symptom.

    The observation to investigate

    Compare COUNT, interrupt level and destination data with the intended job. Form separate hypotheses for symptoms 7, 8 and 9.

    Required behaviour

    Software programmes two blocks; the DMA transforms stream words; only the SBR performs memory transactions.
    Capstone two-block controls and the actual DMA stream path

    What to notice. Software programmes two blocks; the DMA transforms stream words; only the SBR performs memory transactions.

    Check yourself Which block owns a memory read that fails before the DMA receives a word?

    The SBR memory read engine; the DMA has no AXI memory master.

    Your investigation

    Write explicit preconditions for each driver access. For each symptom, identify which block reports first and which register or signal you would read to confirm. Propose one fault hypothesis per symptom and demonstrate a rejecting check before reading the provided injection examples.

    Inputs to start from

    • The DMA and stream-bridge register maps in Programming the DMA Registers.

    • The stream-bridge lesson in the same topic (the stream bridge), for the bridge registers and the stream handshake.

    • Symptoms 7, 8 and 9 in the symptom table.

    Deliverable and pass criterion

    Deliverable. A driver trace table (step, register, value written, precondition) for one clean job, and one hypothesis row per symptom naming the block that reports first and the register you would read to confirm.

    Pass criterion. The clean trace finishes with DONE set, COUNT equal to the programmed length and the interrupt level dropped; for each symptom, your check fails on the observation and passes after your correction.

    Evidence to hand in

    • The driver trace with the precondition of each access.

    • For each of symptoms 7, 8 and 9, the register or signal that first shows the difference from the clean job.

    • The failing and the corrected run for each check.

    Keep your diagnosis in your own report. After the stage checks, compare it with Solutions and run the provided injection checks.

    Related topics

    • Next: Boot Flow and Secure Partition

    • NanoSoC reference tour

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