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Course contents

  • How to Use This Course
  • The NanoSoC Tour
  • Reading Path
  • SoC Glossary10
  • SoC Metrics Reference
  • SoC Cheatsheet
  • What SoC Integration Is12
  • Architecture and Budgets21
  • Memory Maps and Address Decode26
  • Interconnect and Bus Fabrics26
  • Clock and Reset Architecture24
  • Power Architecture21
  • Interrupts, DMA and Peripherals15
  • Memories, Boot and Security21
  • IP Integration and Handoff21
  • Top-Level Verification and Bring-up21
  • Package, Pads and I/O18
  • Chip Signoff and Tapeout18
  • SoC Interview Prep16
  • Capstone: Integrate NanoSoC19
    • Capstone Brief
    • Stage 1: Memory Map and Interconnect
    • Stage 2: Clocks, Resets, Power
    • Stage 3: Interrupts and Boot
    • Stage 4: Verification and Signoff
      • Integration Test Plan Catching All Ten
      • Signoff Manifest and Waiver Ageing
      • Final Manifest Check and Readiness
    • Solutions
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←Stage 4: Verification and Signoff
  1. Topics
  2. SoC Design
  3. Capstone: Integrate NanoSoC
  4. Stage 4: Verification and Signoff
  5. Integration Test Plan Catching All Ten
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    Part 14 of 14, lesson 12 of 19Part 14 of 14/Capstone: Integrate NanoSoC/Lesson 12 of 19All levels

    Integration Test Plan Catching All Ten

    Produce an evidence matrix with a row for each of the ten symptoms.

    The observation to investigate

    Connect each symptom to your hypothesis and a check that passes the required design and rejects the fault you proposed.

    Required behaviour

    The matrix consumes all three earlier stages; clean and failing observations are distinct evidence; every symptom needs a row.
    Capstone evidence matrix with clean and faulty observations

    What to notice. The matrix consumes all three earlier stages; clean and failing observations are distinct evidence; every symptom needs a row.

    Check yourself Which two branches are required before a matrix row can be accepted?

    The clean-data branch must meet the requirement and the proposed faulty branch must show the failure the test is intended to detect.

    Your investigation

    Create columns for symptom ID, requirement, hypothesis, test, observed result and conclusion. Fill result columns from your own runs. Find and inject the fault you think explains each symptom. When tests share a dependency, explain the additional failures rather than assuming each test must identify one fault alone.

    Inputs to start from

    • All ten symptoms in the symptom table.

    • The artefacts from stages 1 to 3: map and link tables, clock, crossing and reset tables, interrupt map and driver trace, boot record.

    • One clean design record to run every check against.

    Deliverable and pass criterion

    Deliverable. An evidence matrix with ten rows and the columns symptom, requirement, hypothesis, test, observed result and conclusion.

    Pass criterion. Every test passes on the clean record and fails on the faulty variant you propose for its row; where one fault trips several tests, the matrix says which test is primary and why the others also fail.

    Evidence to hand in

    • The ten-row matrix, filled from your own runs.

    • For each row, the clean result and the faulty result side by side.

    • A written explanation of every test that fails for more than one row.

    Keep your diagnosis in your own report. After the stage checks, compare it with Solutions and run the provided injection checks.

    Related topics

    • Next: Signoff Manifest and Waiver Ageing

    • NanoSoC reference tour

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    See also

    • Final Manifest Check and Readiness