44 topics in 11 sections. Each entry gives the puzzle count, the easy, medium and hard mix, and the skill the topic tests.
Hands-on interview puzzles that force precise reasoning about SystemVerilog semantics, not memorized rules.
Datatype and Bit Puzzles (6 puzzles; easy/medium/hard 0/6/0). Skill: These puzzles target the places where SystemVerilog silently changes interpretation based on type: 4-state vs 2-state storage, signedness propagation, and operator-specific rules. Strong candidates can predict exact outputs by tracking width, sign, and unknown-bit semantics at every step.
Fork Join Puzzles (6 puzzles; easy/medium/hard 2/4/0). Skill: These puzzles test process-lifetime reasoning under real simulator scheduling. You need to predict when parent code resumes, which child threads keep running, and exactly what scope disable fork can terminate.
Queue and Array Puzzles (6 puzzles; easy/medium/hard 3/3/0). Skill: These puzzles focus on mutable collection semantics that cause real testbench bugs: index shifting, resize copy rules, value-vs-handle behavior, and associative iteration. The goal is to reason about exact final state after each operation, not just API names.
String and Casting Puzzles (6 puzzles; easy/medium/hard 4/2/0). Skill: This set combines string API edge cases with runtime typing semantics. Interviewers use these to test whether you understand index-based string operations, conversion methods, and the exact success/failure behavior of $cast.
Interview-style SystemVerilog/UVM OOP puzzles focused on bugs that appear in real verification code, not classroom examples.
Handle and Copy Puzzles (6 puzzles; easy/medium/hard 2/4/0). Skill: These puzzles test whether you can reason about handle identity, aliasing, and object lifetime under real UVM copy/clone flows. Most failures happen when code looks correct at the top level but a nested handle remains shared, so later mutations silently corrupt expected data.
Virtual Method Puzzles (6 puzzles; easy/medium/hard 4/1/1). Skill: These puzzles target dispatch rules that break real UVM frameworks where most handles are typed as base classes. You are expected to distinguish static binding, dynamic dispatch, and constructor-chain behavior (super.new) without guessing.
Parameterized Class Puzzles (6 puzzles; easy/medium/hard 1/4/1). Skill: These puzzles focus on where specialization boundaries matter: static storage, type compatibility, and factory registration with parameterized classes. Interviewers look for precise statements like 'per specialization' vs 'shared through non-parameterized base' backed by predicted outputs.
Factory Override Puzzles (6 puzzles; easy/medium/hard 1/4/1). Skill: These puzzles test exact UVM factory behavior under competing overrides and mixed object creation styles. You must reason about precedence, path specificity, timing of override registration, and the critical difference between create() and direct new().
Interview-grade puzzles on SystemVerilog scheduler regions, race analysis, clocking block semantics, and semaphore/mailbox deadlocks.
Event Scheduling Puzzles (6 puzzles; easy/medium/hard 2/4/0). Skill: These puzzles force precise reasoning across preponed, active, inactive, NBA, observed, and reactive regions. Most interview misses happen when candidates reason in source-code order instead of scheduler order.
Race Condition Puzzles (6 puzzles; easy/medium/hard 1/5/0). Skill: These puzzles target write-write and read-write races that slip through otherwise clean RTL style. The focus is not just identifying races, but proving exact sampled values and timing outcomes.
Clocking Block Puzzles (6 puzzles; easy/medium/hard 1/4/1). Skill: Clocking blocks remove many races, but only when skew and cycle-delay semantics are understood precisely. These puzzles test sampling versus driving instants, plus ##1 expectations in clocking-domain assertions.
Semaphore & Mailbox Puzzles (6 puzzles; easy/medium/hard 2/4/0). Skill: These puzzles model real bench hangs where nothing crashes but progress stops. The key skill is drawing wait-for graphs across semaphore tokens and mailbox blocking behavior, including try_* APIs and bounded queues.
Puzzle-centric randomization interview drills focused on legal-set counting, solver bias, dist math, solve-before effects, and practical randomize() usage with inline constraints and hooks.
Constraint Solving Order Puzzles (6 puzzles; easy/medium/hard 2/3/1). Skill: Count legal tuples first, then reason about bias: implication and if/else are declarative relations solved together, and branch cardinality drives observed probabilities.
Distribution Puzzles (dist, := vs :/) (6 puzzles; easy/medium/hard 2/4/0). Skill: Translate every dist clause into per-value effective weights, then normalize; mixing := and :/ changes granularity and can dramatically skew outcomes.
solve...before Bias Puzzles (6 puzzles; easy/medium/hard 3/1/2). Skill: Solve-before does not add or remove legal tuples, but it changes frequencies in a defined way (IEEE 1800 18.5.10): the variable named first is chosen uniformly over its values that have a legal completion, then the rest is solved.
randomize() with Puzzles (6 puzzles; easy/medium/hard 1/3/2). Skill: Inline constraints are ANDed with class constraints; understand implication, conditional constraints, foreach, mode toggles, and pre/post_randomize lifecycle to predict pass/fail and outcomes.
24 interview-grade SVA puzzles focused on sequence composition, implication timing, vacuity traps, sampled-value corner cases, reset abort behavior, weak versus strong properties, first_match, and multiclock debugging.
Sequence Puzzles (6 puzzles; easy/medium/hard 0/3/3). Skill: Exact delays, ranges, repetition operators, and sequence-composition semantics under realistic waveforms.
Implication Puzzles (6 puzzles; easy/medium/hard 3/2/1). Skill: Overlapped vs non-overlapped implication, vacuity, and chained consequent timing with real protocol examples.
Temporal Corner Puzzles (6 puzzles; easy/medium/hard 1/4/1). Skill: Sampled-value functions and timing history pitfalls involving $past, $rose, $fell, and $stable.
Assertion Debug Puzzles (6 puzzles; easy/medium/hard 0/4/2). Skill: Debugging real assertion failures and false confidence from reset masking, multiclock sampling, and vacuous threads.
Puzzle-centric interview drills for functional coverage math and semantics: coverpoint bins, cross/binsof/intersect, options behavior, and closure debugging with sampling-time traps.
Covergroup and Coverpoint Puzzles (6 puzzles; easy/medium/hard 1/5/0). Skill: Compute legal bin counts and percentages from sampled traffic, then explain why apparently hit values may not contribute to coverage.
Cross Coverage Puzzles (6 puzzles; easy/medium/hard 1/5/0). Skill: Derive scored cross bin counts precisely, especially when default ignores, binsof/intersect filters, and illegal tuples alter denominator math.
Coverage Options Puzzles (6 puzzles; easy/medium/hard 1/5/0). Skill: Reason about how option.at_least, auto_bin_max, option.weight, per_instance, and type_option change both per-bin and aggregate metrics.
Coverage Closure and Sampling Timing Puzzles (6 puzzles; easy/medium/hard 1/5/0). Skill: Diagnose closure stalls by separating true stimulus gaps from unreachable bins and sampling-region mistakes, then read metrics correctly across instances.
Puzzle-centric drill set for DV interviews: exact reasoning for brain teasers, probability, digital logic construction, and fast bug forensics under pressure.
Classic Brain Teasers (6 puzzles; easy/medium/hard 2/3/1). Skill: Information partitioning, constrained search, and deterministic strategy proofs.
Probability Puzzles (6 puzzles; easy/medium/hard 1/5/0). Skill: Conditioning, expectation recurrences, and Bayes-first reasoning.
Digital Logic Puzzles (6 puzzles; easy/medium/hard 1/5/0). Skill: Gate construction constraints, FSM/counter reasoning, and CDC reliability math.
Debugging Riddles (6 puzzles; easy/medium/hard 1/4/1). Skill: Pinpointing race conditions, RTL/TB semantic traps, and reproducible fixes.
Puzzle-centric DV interview section focused on realistic UVM/TB failures: hangs, phase deadlocks, scoreboard false mismatches, and structured live-debug rounds.
Testbench Debug Puzzles: Why Did the Test Hang? (6 puzzles; easy/medium/hard 1/5/0). Skill: Localize hang roots in sequence-driver handshakes, phase ownership, and missing completion signals.
Deadlock Scenario Puzzles: Objection and Phase Stalls (6 puzzles; easy/medium/hard 2/3/1). Skill: Diagnose deadlocks from objection imbalance, leaked threads, and resource contention primitives.
Scoreboard Puzzles: Mismatch or Ordering Bug? (6 puzzles; easy/medium/hard 1/5/0). Skill: Separate DUT bugs from checker-model bugs: ordering policy, duplication, drops, and end-of-test drain.
Real Interview Rounds: End-to-End Debug Walkthrough (6 puzzles; easy/medium/hard 0/2/4). Skill: Practice a 5-stage interview flow: symptom, hypotheses, instrumentation, root cause, and fix validation.
Interview-style puzzles about UVM as it is used in real testbenches: phase order and objections, the factory and uvm_config_db, sequences and sequencers, and scoreboards, analysis ports and the register layer.
UVM Phases and Objections (6 puzzles; easy/medium/hard 2/3/1). Skill: Interviewers use phase questions to check that you know the direction each phase walks the tree, who holds the simulation open and why an apparently correct component silently does nothing. The puzzles here use UVM 1.2 and focus on ordering across components, drain time, objection extension and creation rules rather than on definitions.
Factory and config_db (6 puzzles; easy/medium/hard 2/2/2). Skill: Configuration problems rarely fail loudly: a path, a type parameter or a phase is slightly off and get() returns 0, or an override never matches. These puzzles drill precedence, scope paths, type keys and timing for uvm_config_db and the factory (UVM 1.2).
Sequences and Sequencers (6 puzzles; easy/medium/hard 2/3/1). Skill: The sequence/driver handshake, arbitration and sequence start-up hide time-zero hangs, wrong exit times and tautological constraints. The puzzles are about what finish_item, grab, p_sequencer and default sequences really do in UVM 1.2.
Analysis, Scoreboards and RAL (6 puzzles; easy/medium/hard 2/2/2). Skill: Scoreboard and register-model questions are about wiring and bookkeeping: which function receives which stream, which value the model holds and which accesses reach the DUT. The puzzles use UVM 1.2 behaviour.
Interview puzzles on the things that break chips after simulation passes: asynchronous and synchronous reset behaviour, reset ordering, clock gating and clock muxes, synchronisers and multi-bit crossings, and how a verification engineer actually catches a CDC or reset bug.
Reset Puzzles (6 puzzles; easy/medium/hard 3/2/1). Skill: Reset looks trivial until you ask which edge sees it, who sees it first, and what the flops hold before it arrives. These puzzles cover asynchronous versus synchronous assertion, the reset synchroniser, ordering across reset domains, power-on state and the first cycles after release.
Clock Gating & Clock Mux Puzzles (6 puzzles; easy/medium/hard 1/4/1). Skill: A clock is a signal like any other until you gate or switch it. These puzzles are about the pulses a gate can create: truncated pulses, runt pulses, extra edges, and the structures (latch-based gating, safe clock switching) that prevent them.
CDC Basics Puzzles (6 puzzles; easy/medium/hard 2/2/2). Skill: Single-bit and multi-bit crossings, the arithmetic of metastability, and the structures that make data safe to use on the other side: toggle synchronisers, gray code, handshakes, FIFO pointers and data coherency.
Verifying CDC & Reset Puzzles (6 puzzles; easy/medium/hard 2/2/2). Skill: Simulation is the weakest tool for clock-domain and reset bugs: it is zero-delay, 4-state, and usually driven by clean clocks. These puzzles are about what a bench cannot see, how to make it see more, and the traps in the checks themselves.
Interview puzzles on the protocols a DV engineer is asked about: valid/ready handshakes (stall, drop, skid buffers), AMBA APB, AXI4 channels, ordering and burst rules, and FIFO, arbitration and credit flow control.
Valid/Ready Handshake Puzzles (6 puzzles; easy/medium/hard 3/1/2). Skill: Stalls, dropped valids, unstable payloads, mutual-wait deadlocks, registered ready and skid buffers. Most interview misses come from reasoning about one cycle instead of the previous cycle's handshake state.
APB Protocol Puzzles (6 puzzles; easy/medium/hard 2/3/1). Skill: AMBA APB (APB3/APB4): setup and access phases, PREADY wait states, PSLVERR validity, back-to-back transfers and signal stability. The recurring trap is treating APB as pipelined or sampling a signal outside the one cycle where it is defined.
AXI Protocol Puzzles (6 puzzles; easy/medium/hard 1/4/1). Skill: AXI4 channel independence, per-ID ordering, WRAP and INCR address rules, the 4 KB boundary, WLAST and response codes. Every puzzle states the AXI version it assumes.
FIFO, Arbitration and Credit Puzzles (6 puzzles; easy/medium/hard 2/2/2). Skill: FIFO sizing and flag timing, Gray-coded asynchronous pointers, round-robin fairness, credit-based flow control and circular-wait deadlock.