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Course contents

  • How to Use This Puzzle Bank
  • SystemVerilog Language Puzzles25
  • Difficulty Guide
  • Full Topic Map
  • Interview-Day Tips
  • Study Route: One Week Before the Interview
  • Study Route: Two Weeks
  • Study Route: Four Weeks (Full Course)4
  • OOP & Testbench Puzzles25
  • Concurrency & Timing Puzzles25
  • Randomization & Constraint Puzzles25
  • SVA Assertion Puzzles25
    • Sequence Puzzles
      • Exact Delay Then Bounded Hold
      • Goto Repetition With Sparse Events
      • Nonconsecutive Repetition [=2]
      • Sequence and Operator
      • first_match in an Antecedent
      • within Window Length Off-By-One
    • Implication Puzzles
    • Temporal Corner Puzzles
    • Assertion Debug Puzzles
    • SVA Assertion Puzzles: Tricky Q&A
  • Functional Coverage Puzzles25
  • Logic & Aptitude Puzzles25
  • Scenario & Debug Puzzles25
  • UVM Testbench Puzzles25
  • Clock, Reset & CDC Puzzles25
  • Bus and Interface Protocol Puzzles25
  • Interview Prep: Puzzle Rounds7
  • DV Puzzle Cheatsheet
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←SVA Assertion Puzzles
  1. Topics
  2. DV Interview Puzzles
  3. SVA Assertion Puzzles
  4. Sequence Puzzles
On this page

    VLSI DV Interview PuzzlesAll levels

    Sequence Puzzles

    Exact delays, ranges, repetition operators, and sequence-composition semantics under realistic waveforms.

    • 6topics
    • 6lessons

    Topics in this section

    1. 1Exact Delay Then Bounded Hold1 lesson
    2. 2Goto Repetition With Sparse Events1 lesson
    3. 3Nonconsecutive Repetition [=2]1 lesson
    4. 4Sequence and Operator1 lesson
    5. 5first_match in an Antecedent1 lesson
    6. 6within Window Length Off-By-One1 lesson

    About this puzzle set

    Exact delays, ranges, repetition operators, and sequence-composition semantics under realistic waveforms.

    Puzzles in this topic

    Diagram
    1. Exact Delay Then Bounded Hold  [Medium]
    2. Goto Repetition With Sparse Events  [Medium]
    3. Nonconsecutive Repetition [=2]  [Hard]
    4. Sequence and Operator  [Medium]
    5. first_match in an Antecedent  [Hard]
    6. within Window Length Off-By-One  [Hard]

    Work each puzzle before reading the solution: predict the exact output or answer, name the rule that governs it, then check yourself.

    Related topics

    • SVA Assertion Puzzles section

    • VLSI DV Interview Puzzles hub

    PreviousNext: Exact Delay Then Bounded Hold

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    See also

    • Implication Puzzles
    • Temporal Corner Puzzles
    • Assertion Debug Puzzles