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Course contents

  • How to Use This Puzzle Bank
  • SystemVerilog Language Puzzles25
  • Difficulty Guide
  • Full Topic Map
  • Interview-Day Tips
  • Study Route: One Week Before the Interview
  • Study Route: Two Weeks
  • Study Route: Four Weeks (Full Course)4
  • OOP & Testbench Puzzles25
  • Concurrency & Timing Puzzles25
  • Randomization & Constraint Puzzles25
    • Constraint Solving Order Puzzles
    • Distribution Puzzles (`dist`, `:=` vs `:/`)
    • solve...before Bias Puzzles
      • Classic a->b Bias Shift
      • Three-Branch Kind Selection
      • Reverse Bias with solve b before a
      • m<n Cardinality Bias
      • Mode Branch Collapse Under Extra Relation
      • Three-Variable solve-before Chain
    • randomize() with Puzzles
    • Randomization & Constraint Puzzles: Tricky Q&A
  • SVA Assertion Puzzles25
  • Functional Coverage Puzzles25
  • Logic & Aptitude Puzzles25
  • Scenario & Debug Puzzles25
  • UVM Testbench Puzzles25
  • Clock, Reset & CDC Puzzles25
  • Bus and Interface Protocol Puzzles25
  • Interview Prep: Puzzle Rounds7
  • DV Puzzle Cheatsheet
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←Randomization & Constraint Puzzles
  1. Topics
  2. DV Interview Puzzles
  3. Randomization & Constraint Puzzles
  4. solve...before Bias Puzzles
On this page

    VLSI DV Interview PuzzlesAll levels

    solve...before Bias Puzzles

    Solve-before does not add or remove legal tuples, but it changes frequencies in a defined way (IEEE 1800 18.5.10): the variable named first is chosen uniformly over its values that have a legal completion, then the rest is solved.

    • 6topics
    • 6lessons

    Topics in this section

    1. 1Classic a->b Bias Shift1 lesson
    2. 2Three-Branch Kind Selection1 lesson
    3. 3Reverse Bias with solve b before a1 lesson
    4. 4m<n Cardinality Bias1 lesson
    5. 5Mode Branch Collapse Under Extra Relation1 lesson
    6. 6Three-Variable solve-before Chain1 lesson

    About this puzzle set

    Solve-before does not add or remove legal tuples, but it changes frequencies in a defined way (IEEE 1800 18.5.10): the variable named first is chosen uniformly over its values that have a legal completion, then the rest is solved.

    Puzzles in this topic

    Diagram
    1. Classic a->b Bias Shift  [Easy]
    2. Three-Branch Kind Selection  [Medium]
    3. Reverse Bias with solve b before a  [Easy]
    4. m<n Cardinality Bias  [Easy]
    5. Mode Branch Collapse Under Extra Relation  [Hard]
    6. Three-Variable solve-before Chain  [Hard]

    Work each puzzle before reading the solution: predict the exact output or answer, name the rule that governs it, then check yourself.

    Constraint solve order and dependency flow

    Diagram
    CONSTRAINT SOLVE ORDER
    
    rand bit [3:0] burst_len;
    rand bit [7:0] addr;
    
    constraints:
      burst_len inside {[1:8]};
      addr % burst_len == 0;
      solve burst_len before addr;
    
    solver picks burst_len first
                then chooses addr satisfying alignment
    
    Explicit solve order reduces ambiguity in interview puzzles.

    Related topics

    • Randomization & Constraint Puzzles section

    • VLSI DV Interview Puzzles hub

    PreviousNext: Classic a->b Bias Shift

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    Up nextClassic a->b Bias Shift

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    See also

    • Constraint Solving Order Puzzles
    • Distribution Puzzles (`dist`, `:=` vs `:/`)
    • randomize() with Puzzles