VLSI DV Interview Puzzles · All levels
Queue and Array Puzzles
These puzzles focus on mutable collection semantics that cause real testbench bugs: index shifting, resize copy rules, value-vs-handle behavior, and associative iteration. The goal is to reason about exact final state after each operation, not just API names.
About this puzzle set
These puzzles focus on mutable collection semantics that cause real testbench bugs: index shifting, resize copy rules, value-vs-handle behavior, and associative iteration. The goal is to reason about exact final state after each operation, not just API names.
Puzzles in this topic
diagram
1. Queue Mutation Plus Dynamic Resize [Easy]
2. Queue Assignment Copies by Value [Easy]
3. Pop from Empty Queue [Medium]
4. Dynamic Array Resize with Class Handles [Hard]
5. Associative Array Iteration Order [Medium]
6. Locator Methods Return New Queues [Hard]Work each puzzle before reading the solution: predict the exact output or answer, name the rule that governs it, then check yourself.
SV scheduling regions at puzzle scale
diagram
SYSTEMVERILOG EVENT REGIONS (SIMPLIFIED ORDER)
time slot T
|
+--> ACTIVE : blocking statements, RHS sampling
+--> INACTIVE : #0 queued work
+--> NBA : non-blocking LHS updates commit
+--> OBSERVED : assertions sample stable design values
+--> REACTIVE : testbench/program reaction code
If behavior looks impossible, ask: "Which region saw which value?"