Course map
- 1 lesson
Starts with How to Use This Puzzle Bank
- 25 lessons
Starts with X-Bit Comparisons and Mixed Arithmetic
- 1 lesson
Starts with Difficulty Guide
- 1 lesson
Starts with Full Topic Map
- 1 lesson
Starts with Interview-Day Tips
- 1 lesson
Starts with Study Route: One Week Before the Interview
- 1 lesson
Starts with Study Route: Two Weeks
- 4 lessons
Starts with Four-Week Route: Week 1
- 25 lessons
Starts with Shallow Copy in Nested Payload
- 25 lessons
Starts with Assertion Samples Preponed Values
- 25 lessons
Starts with Implication vs Partitioned Branches
- 25 lessons
Starts with Exact Delay Then Bounded Hold
- 25 lessons
Starts with Auto vs explicit bins with illegal transition context
- 25 lessons
Starts with 9 Balls, 1 Heavier, 2 Weighings
- 25 lessons
Starts with Handshake Hang: Missing item_done on One Branch
- 25 lessons
Starts with Which Way Do the Phases Walk the Tree
- 25 lessons
Starts with A Reset Pulse Between Two Clock Edges
- 25 lessons
Starts with Counting Transfers in a Valid/Ready Trace
- 7 lessons
Starts with Framework for Any Unseen Puzzle
- 1 lesson
Starts with DV Puzzle Cheatsheet
About this course
What this course is
This is a puzzle bank, not a lecture series. It has 264 interview-style puzzles in 11 sections and 44 topics. Each page gives you a prompt and, usually, code. You predict the answer first, then compare it with a worked solution, the exact answer, the trap the interviewer is testing, and the follow-up they would ask next.
The goal is not to remember answers. The goal is to be able to reason from the rule (types, scheduling regions, solver semantics, sampling) to an exact prediction in a few minutes, say it clearly, and defend it when the interviewer changes the snippet.
Who it is for
Candidates preparing for design-verification, SystemVerilog or UVM interviews, from new graduate to experienced engineer changing company.
Engineers who use the language every day but have not been asked to predict an exact output on a whiteboard for years.
Interviewers who want a bank of puzzles with known answers and known follow-ups.
If you are new to SystemVerilog, learn the topic in the teaching courses linked at the bottom of this page first, then come back. The puzzles assume you know the syntax and test whether you know the semantics.
The sections
Counts below are computed from the course data, so they are always the real number of topics and puzzles.
Section | Topics | Puzzles | Easy / Medium / Hard | What it trains |
|---|---|---|---|---|
4 | 24 | 9 / 15 / 0 | Hands-on interview puzzles that force precise reasoning about SystemVerilog semantics, not memorized rules. | |
4 | 24 | 8 / 13 / 3 | Interview-style SystemVerilog/UVM OOP puzzles focused on bugs that appear in real verification code, not classroom examples. | |
4 | 24 | 6 / 17 / 1 | Interview-grade puzzles on SystemVerilog scheduler regions, race analysis, clocking block semantics, and semaphore/mailbox deadlocks. | |
4 | 24 | 8 / 11 / 5 | Puzzle-centric randomization interview drills focused on legal-set counting, solver bias, dist math, solve-before effects, and practical randomize() usage with inline constraints and hooks. | |
4 | 24 | 4 / 13 / 7 | 24 interview-grade SVA puzzles focused on sequence composition, implication timing, vacuity traps, sampled-value corner cases, reset abort behavior, weak versus strong properties, first_match, and multiclock debugging. | |
4 | 24 | 4 / 20 / 0 | Puzzle-centric interview drills for functional coverage math and semantics: coverpoint bins, cross/binsof/intersect, options behavior, and closure debugging with sampling-time traps. | |
4 | 24 | 5 / 17 / 2 | Puzzle-centric drill set for DV interviews: exact reasoning for brain teasers, probability, digital logic construction, and fast bug forensics under pressure. | |
4 | 24 | 4 / 15 / 5 | Puzzle-centric DV interview section focused on realistic UVM/TB failures: hangs, phase deadlocks, scoreboard false mismatches, and structured live-debug rounds. | |
4 | 24 | 8 / 10 / 6 | Interview-style puzzles about UVM as it is used in real testbenches: phase order and objections, the factory and uvm_config_db, sequences and sequencers, and scoreboards, analysis ports and the register layer. | |
4 | 24 | 8 / 10 / 6 | Interview puzzles on the things that break chips after simulation passes: asynchronous and synchronous reset behaviour, reset ordering, clock gating and clock muxes, synchronisers and multi-bit crossings, and how a verification engineer actually catches a CDC or reset bug. | |
4 | 24 | 8 / 10 / 6 | Interview puzzles on the protocols a DV engineer is asked about: valid/ready handshakes (stall, drop, skid buffers), AMBA APB, AXI4 channels, ordering and burst rules, and FIFO, arbitration and credit flow control. |
Total: 264 puzzles, 72 easy, 151 medium and 41 hard. Every section also has a tricky Q&A page for rapid-fire rehearsal, and the interview prep pages contain full live-interview walkthroughs.
How a puzzle page works
Every puzzle page has the same parts, in this order. Use them in this order too.
Puzzle: the prompt, with its difficulty and topic. Read it and start your timer (see the difficulty guide).
Code: the snippet. Predict before you scroll.
Hint: one nudge. Using it costs one point on the self-score.
Step-by-step solution: the trace, value by value or region by region.
Answer: the exact output or the exact yes/no/number.
How this was checked: whether the answer came from a tool run, from a small model of the rule, or from reasoning only. Read how to use this bank for what each form means.
Why candidates get it wrong: the actual interview signal, the specific mistake people make.
Interviewer follow-up: how the interviewer will change the puzzle, with a model answer.
Say it out loud: a short spoken answer. Record yourself and compare.
Learn links: lessons in the teaching courses that explain the idea behind the puzzle. Not every puzzle has every part; the checked-by line and the spoken answer are added section by section.
Three study routes
Pick the route that matches the time you have. Every puzzle id is a link. E, M and H after a link mean easy, medium and hard. Each route ends with the interview pages, because knowing the answer is only half of an interview: the other half is saying it clearly under time pressure.
Route | Time | Daily load | Covers |
|---|---|---|---|
One week before the interview | 7 days | About 40 to 60 minutes | The highest-yield easy and medium puzzles of every section, the framework and the live-interview pages |
Two weeks | 10 days | About 60 to 90 minutes | About eight puzzles per section, including the one-week set, plus all live-interview pages and a mock round |
Four weeks (full course) | 4 weeks, 4 study days + 1 review day each | About 60 to 90 minutes | All 264 puzzles, section Q&A, all scenarios and a full mock round |
Route 1: one week before the interview
Three to four puzzles per section, chosen because they test a rule that comes up again and again. Overview below; the full one-week route lists every puzzle id by day.
Day | Work | Puzzles |
|---|---|---|
Day 1 | 8 | |
Day 2 | Concurrency & Timing Puzzles; Randomization & Constraint Puzzles | 8 |
Day 3 | 8 | |
Day 4 | 7 | |
Day 5 | UVM Testbench Puzzles; Clock, Reset & CDC Puzzles; Bus and Interface Protocol Puzzles | 11 |
Day 6 | Framework for any unseen puzzle; live-interview pages | - |
Day 7 | Cheatsheet, interview-day tips, re-do misses | - |
Route 2: two weeks
The one-week puzzles plus about four more per section, spread across the topics, easy and medium first, over ten days. The overview is below; the full two-week route lists every puzzle id by day.
Week | Days | Sections | Puzzles |
|---|---|---|---|
Week 1 | Days 1 to 5 | SystemVerilog Language Puzzles; OOP & Testbench Puzzles; Concurrency & Timing Puzzles; Randomization & Constraint Puzzles; SVA Assertion Puzzles; Functional Coverage Puzzles | 48 |
Week 2 | Days 6 to 8, then day 9 interview prep and day 10 mock round | Logic & Aptitude Puzzles; Scenario & Debug Puzzles; UVM Testbench Puzzles; Clock, Reset & CDC Puzzles; Bus and Interface Protocol Puzzles | 40 |
Route 3: four weeks (full course)
Every topic and every puzzle: four study days a week with a review day on the fifth. The overview is below; the full four-week route has one page per week with every puzzle id by day.
Where to go next
How to use this puzzle bank: the attempt-cold loop, how to use the spoken answer, how to read the checked-by line.
Difficulty guide: what easy, medium and hard mean in minutes, and the 0 to 4 self-score.
Full topic map: every topic and the skill it tests.
Interview-day tips: thinking aloud, clarifying questions, handling an unknown.
Interview prep: a framework for unseen puzzles and 6 live-interview scenarios.
Cheatsheet: the rules that decide most puzzles, section by section.