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Course contents

  • How to Use This Puzzle Bank
  • SystemVerilog Language Puzzles25
  • Difficulty Guide
  • Full Topic Map
  • Interview-Day Tips
  • Study Route: One Week Before the Interview
  • Study Route: Two Weeks
  • Study Route: Four Weeks (Full Course)4
  • OOP & Testbench Puzzles25
  • Concurrency & Timing Puzzles25
  • Randomization & Constraint Puzzles25
  • SVA Assertion Puzzles25
  • Functional Coverage Puzzles25
  • Logic & Aptitude Puzzles25
    • Classic Brain Teasers
    • Probability Puzzles
    • Digital Logic Puzzles
      • Build XOR Using Only 2:1 MUXes
      • One-Cycle Pulse Across Clock Domains
      • Minimum NAND Gates for XOR
      • Overlapping 1011 Sequence Detector
      • Mod-6 Counter Behavior Check
      • Metastability MTBF Improvement Estimate
    • Debugging Riddles
    • Logic & Aptitude Puzzles: Tricky Q&A
  • Scenario & Debug Puzzles25
  • UVM Testbench Puzzles25
  • Clock, Reset & CDC Puzzles25
  • Bus and Interface Protocol Puzzles25
  • Interview Prep: Puzzle Rounds7
  • DV Puzzle Cheatsheet
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←Logic & Aptitude Puzzles
  1. Topics
  2. DV Interview Puzzles
  3. Logic & Aptitude Puzzles
  4. Digital Logic Puzzles
On this page

    VLSI DV Interview PuzzlesAll levels

    Digital Logic Puzzles

    Gate construction constraints, FSM/counter reasoning, and CDC reliability math.

    • 6topics
    • 6lessons

    Topics in this section

    1. 1Build XOR Using Only 2:1 MUXes1 lesson
    2. 2One-Cycle Pulse Across Clock Domains1 lesson
    3. 3Minimum NAND Gates for XOR1 lesson
    4. 4Overlapping 1011 Sequence Detector1 lesson
    5. 5Mod-6 Counter Behavior Check1 lesson
    6. 6Metastability MTBF Improvement Estimate1 lesson

    About this puzzle set

    Gate construction constraints, FSM/counter reasoning, and CDC reliability math.

    Puzzles in this topic

    Diagram
    1. Build XOR Using Only 2:1 MUXes  [Easy]
    2. One-Cycle Pulse Across Clock Domains  [Medium]
    3. Minimum NAND Gates for XOR  [Medium]
    4. Overlapping 1011 Sequence Detector  [Medium]
    5. Mod-6 Counter Behavior Check  [Medium]
    6. Metastability MTBF Improvement Estimate  [Medium]

    Work each puzzle before reading the solution: predict the exact output or answer, name the rule that governs it, then check yourself.

    Related topics

    • Logic & Aptitude Puzzles section

    • VLSI DV Interview Puzzles hub

    PreviousNext: Build XOR Using Only 2:1 MUXes

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    See also

    • Classic Brain Teasers
    • Probability Puzzles
    • Debugging Riddles