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Course contents

  • How to Use This Puzzle Bank
  • SystemVerilog Language Puzzles25
    • Datatype and Bit Puzzles
      • X-Bit Comparisons and Mixed Arithmetic
      • Signed vs Unsigned Comparison Trap
      • Type Cast Controls Sign Extension
      • Signed Part-Select Is Still Unsigned
      • X Collapse into 2-State `int`
      • Expression Width Drops the Carry
    • Fork Join Puzzles
    • Queue and Array Puzzles
    • String and Casting Puzzles
    • SystemVerilog Language Puzzles: Tricky Q&A
  • Difficulty Guide
  • Full Topic Map
  • Interview-Day Tips
  • Study Route: One Week Before the Interview
  • Study Route: Two Weeks
  • Study Route: Four Weeks (Full Course)4
  • OOP & Testbench Puzzles25
  • Concurrency & Timing Puzzles25
  • Randomization & Constraint Puzzles25
  • SVA Assertion Puzzles25
  • Functional Coverage Puzzles25
  • Logic & Aptitude Puzzles25
  • Scenario & Debug Puzzles25
  • UVM Testbench Puzzles25
  • Clock, Reset & CDC Puzzles25
  • Bus and Interface Protocol Puzzles25
  • Interview Prep: Puzzle Rounds7
  • DV Puzzle Cheatsheet
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←Datatype and Bit Puzzles
  1. Topics
  2. DV Interview Puzzles
  3. SystemVerilog Language Puzzles
  4. Datatype and Bit Puzzles
  5. X-Bit Comparisons and Mixed Arithmetic
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    VLSI DV Interview PuzzlesAll levels

    X-Bit Comparisons and Mixed Arithmetic

    Predict each display line exactly, including where x appears, and explain why.

    Puzzle

    Difficulty: Medium · Puzzle 1 of 6 · Topic: Datatype and Bit Puzzles

    Predict each display line exactly, including where x appears, and explain why.

    Code

    p1.sv
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    module p1;
      logic [3:0] a = 4'b1x01;
      bit   [3:0] b = 4'b1x01;
      logic signed [3:0] s = 4'b1100; // -4
      logic [7:0] u = 8'd250;
      initial begin
        $display("eq=%b", (a == 4'b1001));
        $display("caseeq=%0d", (a === 4'b1x01));
        $display("b=%b", b);
        $display("s>>>1=%0d s>>1=%0d", (s >>> 1), (s >> 1));
        $display("mix=%0d", u + (-8'sd10));
      end
    endmodule

    Hint

    Treat each expression independently: comparison operator, storage type, and shift operator each have different rules. The last line is a signed/unsigned promotion puzzle.

    Step-by-step solution

    Diagram
    1) `a == 4'b1001` returns x because `a` contains an unknown bit that affects logical equality.
    2) `a === 4'b1x01` returns 1 because case equality matches X/Z explicitly.
    3) `b` is 2-state, so assignment collapses x to 0 and prints 1001.
    4) `s` is -4; arithmetic shift `>>> 1` gives -2, while logical shift `>> 1` zero-fills and gives +6.
    5) In `u + (-8'sd10)`, unsigned `u` forces unsigned arithmetic at 8 bits, so 250 + 246 wraps to 240.

    Answer

    Answer: eq=x, caseeq=1, b=1001, s>>>1=-2 s>>1=6, mix=240

    How this was checked

    Checked by running the code in Icarus Verilog 13 and Verilator 5; the printed output supports the answer above. Icarus (4-state) shows the x from == and the exact === match. Verilator is 2-state, so the x was already turned into 0 when a was loaded and eq and caseeq differ from the 4-state answer; only a 4-state tool shows the x rules.

    Why candidates get it wrong

    `b = 4'b1x01` silently becomes 1001, and `s >> 1` prints 6, not -2: `>>` is a logical shift even on a signed value, only `>>>` sign-fills.

    Interviewer follow-up

    How would the `mix` result change if you wrote `$signed(u) + (-8'sd10)`? Model answer: both operands are now signed 8-bit, so u = 250 is read as -6 and -6 + -10 = -16, printed as -16 instead of 240.

    Say it out loud

    I would take the lines one at a time, because each operator has its own rule. Equality on a value with an unknown bit gives x, case equality matches the x exactly and gives 1, the two-state variable has already turned the x into 0 so it prints 1001, and the logical shift of minus four gives 6 while the arithmetic shift gives minus two. The last line is unsigned because one operand is unsigned, so 250 plus 246 wraps to 240. The trap is that this depends on the tool: a two-state simulator like Verilator already lost the x, so I would run it on a four-state tool, and I would check the shift and the signedness of each operand.

    Related topics

    • 4-State vs 2-State Types

    • Equality, Case Equality & Wildcards

    • Shifts, Concatenation & Streaming

    • Back to Datatype and Bit Puzzles

    • SystemVerilog Language Puzzles section

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    See also

    • Signed vs Unsigned Comparison Trap
    • Type Cast Controls Sign Extension
    • Signed Part-Select Is Still Unsigned