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Course contents

  • How to Use This Puzzle Bank
  • SystemVerilog Language Puzzles25
  • Difficulty Guide
  • Full Topic Map
  • Interview-Day Tips
  • Study Route: One Week Before the Interview
  • Study Route: Two Weeks
  • Study Route: Four Weeks (Full Course)4
  • OOP & Testbench Puzzles25
  • Concurrency & Timing Puzzles25
  • Randomization & Constraint Puzzles25
    • Constraint Solving Order Puzzles
      • Implication vs Partitioned Branches
      • Bidirectional Solving of x+y==10
      • if-else with Overlap on One Value
      • randc Cycle with a Skipped Value
      • Width Wrap in a Sum Constraint
      • Array Size Coupled to Content
    • Distribution Puzzles (`dist`, `:=` vs `:/`)
    • solve...before Bias Puzzles
    • randomize() with Puzzles
    • Randomization & Constraint Puzzles: Tricky Q&A
  • SVA Assertion Puzzles25
  • Functional Coverage Puzzles25
  • Logic & Aptitude Puzzles25
  • Scenario & Debug Puzzles25
  • UVM Testbench Puzzles25
  • Clock, Reset & CDC Puzzles25
  • Bus and Interface Protocol Puzzles25
  • Interview Prep: Puzzle Rounds7
  • DV Puzzle Cheatsheet
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←Randomization & Constraint Puzzles
  1. Topics
  2. DV Interview Puzzles
  3. Randomization & Constraint Puzzles
  4. Constraint Solving Order Puzzles
On this page

    VLSI DV Interview PuzzlesAll levels

    Constraint Solving Order Puzzles

    Count legal tuples first, then reason about bias: implication and if/else are declarative relations solved together, and branch cardinality drives observed probabilities.

    • 6topics
    • 6lessons

    Topics in this section

    1. 1Implication vs Partitioned Branches1 lesson
    2. 2Bidirectional Solving of x+y==101 lesson
    3. 3if-else with Overlap on One Value1 lesson
    4. 4randc Cycle with a Skipped Value1 lesson
    5. 5Width Wrap in a Sum Constraint1 lesson
    6. 6Array Size Coupled to Content1 lesson

    About this puzzle set

    Count legal tuples first, then reason about bias: implication and if/else are declarative relations solved together, and branch cardinality drives observed probabilities.

    Puzzles in this topic

    Diagram
    1. Implication vs Partitioned Branches  [Medium]
    2. Bidirectional Solving of x+y==10  [Easy]
    3. if-else with Overlap on One Value  [Easy]
    4. randc Cycle with a Skipped Value  [Medium]
    5. Width Wrap in a Sum Constraint  [Hard]
    6. Array Size Coupled to Content  [Medium]

    Work each puzzle before reading the solution: predict the exact output or answer, name the rule that governs it, then check yourself.

    Constraint solve order and dependency flow

    Diagram
    CONSTRAINT SOLVE ORDER
    
    rand bit [3:0] burst_len;
    rand bit [7:0] addr;
    
    constraints:
      burst_len inside {[1:8]};
      addr % burst_len == 0;
      solve burst_len before addr;
    
    solver picks burst_len first
                then chooses addr satisfying alignment
    
    Explicit solve order reduces ambiguity in interview puzzles.

    Related topics

    • Randomization & Constraint Puzzles section

    • VLSI DV Interview Puzzles hub

    PreviousNext: Implication vs Partitioned Branches

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    See also

    • Distribution Puzzles (`dist`, `:=` vs `:/`)
    • solve...before Bias Puzzles
    • randomize() with Puzzles