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Course contents

  • How to Use This Puzzle Bank
  • SystemVerilog Language Puzzles25
  • Difficulty Guide
  • Full Topic Map
  • Interview-Day Tips
  • Study Route: One Week Before the Interview
  • Study Route: Two Weeks
  • Study Route: Four Weeks (Full Course)4
  • OOP & Testbench Puzzles25
  • Concurrency & Timing Puzzles25
  • Randomization & Constraint Puzzles25
  • SVA Assertion Puzzles25
  • Functional Coverage Puzzles25
  • Logic & Aptitude Puzzles25
  • Scenario & Debug Puzzles25
  • UVM Testbench Puzzles25
  • Clock, Reset & CDC Puzzles25
  • Bus and Interface Protocol Puzzles25
  • Interview Prep: Puzzle Rounds7
  • DV Puzzle Cheatsheet
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←DV Interview Puzzles
  1. Topics
  2. DV Interview Puzzles
  3. Difficulty Guide
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    VLSI DV Interview PuzzlesAll levels

    Difficulty Guide

    Easy, medium and hard defined by the time a prepared candidate needs, with a 0 to 4 self-scoring rubric.

    Difficulty in minutes

    A difficulty tag is a promise about time and about what a good answer contains. It is measured for a candidate who has prepared, not for a beginner.

    Level

    Time for a prepared candidate

    What is expected

    Typical shape

    Easy

    3 minutes

    The right answer.

    One rule in play. Expected if you know the language or the tool flow.

    Medium

    6 to 8 minutes

    The answer and the why: you name the rule that decides it.

    Two rules interact (for example signedness and shift, solve order and distribution, sampling and reset).

    Hard

    10 to 15 minutes

    The answer, the why, the trap and a fix.

    A subtle ordering, scheduling or solver interaction that experienced engineers also miss.

    Section

    Easy

    Medium

    Hard

    SystemVerilog Language Puzzles

    9

    15

    0

    OOP & Testbench Puzzles

    8

    13

    3

    Concurrency & Timing Puzzles

    6

    17

    1

    Randomization & Constraint Puzzles

    8

    11

    5

    SVA Assertion Puzzles

    4

    13

    7

    Functional Coverage Puzzles

    4

    20

    0

    Logic & Aptitude Puzzles

    5

    17

    2

    Scenario & Debug Puzzles

    4

    15

    5

    UVM Testbench Puzzles

    8

    10

    6

    Clock, Reset & CDC Puzzles

    8

    10

    6

    Bus and Interface Protocol Puzzles

    8

    10

    6

    Self-scoring rubric: 0 to 4

    Score every attempt before you read the solution. Be strict. The score tells you what to do next.

    Score

    Meaning

    What to do

    0

    No idea. You could not start.

    Read the hint and solution, then re-attempt cold tomorrow.

    1

    Right idea, wrong result. You found the topic but made an error in the trace.

    Find the line where the trace went wrong. Re-attempt in two days.

    2

    Right result, no reason. You may have guessed or recalled it.

    Treat it as a miss. Write the rule in one sentence, then re-attempt in two days.

    3

    Right result and the reason. You named the rule.

    Good. Add the trap: what does a wrong answer look like?

    4

    Right result, reason, the trap and a fix. You also named what changes if the snippet is mutated.

    Done. Revisit once, a week later, as a check.

    If you used the hint, take one point off. A hard puzzle needs a 4 to count as done. For an easy puzzle a 3 is enough. Track your score per section: the lowest section average is where tomorrow's hour goes.

    How a single puzzle escalates

    Interviewers rarely switch puzzles; they mutate one. Change blocking to nonblocking, add disable iff, flip |-> to |=>, add solve...before, or move the sample point. Each puzzle's follow-up shows the escalation to expect, so an easy puzzle in your first minutes can turn into a hard one in the next five.

    • Easy then medium: the same snippet, one more rule added.

    • Medium then hard: the interviewer asks what changes if the order, the clock or the tool changes.

    • Hard then discussion: the interviewer asks how you would prove it, check it or fix it in a real testbench.

    Related topics

    • VLSI DV Interview Puzzles hub

    • How to use this puzzle bank

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    See also

    • How to Use This Puzzle Bank
    • SystemVerilog Language Puzzles
    • Interview-Day Tips