Debugging real assertion failures and false confidence from reset masking, multiclock sampling, and vacuous threads.
1. disable iff Reset Glitch Hides a Lost Grant [Medium]
2. Multiclock Ack Visibility [Hard]
3. Weak vs Strong at End of Simulation [Hard]
4. Overlapping Attempts Share One Grant [Medium]
5. $rose Consumed During Reset [Medium]
6. Intersect Requirement in Dual Checks [Medium]Work each puzzle before reading the solution: predict the exact output or answer, name the rule that governs it, then check yourself.