Skip to content
DenseChip
Learn
PracticeCode labInterview

DenseChip

Navigate

Menu

LearnPracticeCode labInterview

Tools

All toolsSV editorCode repoResume
DenseChip

Practice, courses, and chip-design tools in one focused workspace.

LearnPracticeCode labInterviewToolsLearning paths

© 2026 DenseChip

AboutRoadmapCareersInternshipsFAQContactPrivacyTerms
Skip to lesson

Course contents

  • How to Use This Puzzle Bank
  • SystemVerilog Language Puzzles25
  • Difficulty Guide
  • Full Topic Map
  • Interview-Day Tips
  • Study Route: One Week Before the Interview
  • Study Route: Two Weeks
  • Study Route: Four Weeks (Full Course)4
  • OOP & Testbench Puzzles25
  • Concurrency & Timing Puzzles25
  • Randomization & Constraint Puzzles25
  • SVA Assertion Puzzles25
    • Sequence Puzzles
    • Implication Puzzles
    • Temporal Corner Puzzles
      • $past Startup History Hole
      • $rose Sampled on Clock Edge
      • $fell Is an Event, Not a Level
      • $stable Repeated Hold Check
      • $past After Reset Release
      • Vector $rose Sampling Trap
    • Assertion Debug Puzzles
    • SVA Assertion Puzzles: Tricky Q&A
  • Functional Coverage Puzzles25
  • Logic & Aptitude Puzzles25
  • Scenario & Debug Puzzles25
  • UVM Testbench Puzzles25
  • Clock, Reset & CDC Puzzles25
  • Bus and Interface Protocol Puzzles25
  • Interview Prep: Puzzle Rounds7
  • DV Puzzle Cheatsheet
Loading lesson

←SVA Assertion Puzzles
  1. Topics
  2. DV Interview Puzzles
  3. SVA Assertion Puzzles
  4. Temporal Corner Puzzles
On this page

    VLSI DV Interview PuzzlesAll levels

    Temporal Corner Puzzles

    Sampled-value functions and timing history pitfalls involving $past, $rose, $fell, and $stable.

    • 6topics
    • 6lessons

    Topics in this section

    1. 1$past Startup History Hole1 lesson
    2. 2$rose Sampled on Clock Edge1 lesson
    3. 3$fell Is an Event, Not a Level1 lesson
    4. 4$stable Repeated Hold Check1 lesson
    5. 5$past After Reset Release1 lesson
    6. 6Vector $rose Sampling Trap1 lesson

    About this puzzle set

    Sampled-value functions and timing history pitfalls involving $past, $rose, $fell, and $stable.

    Puzzles in this topic

    Diagram
    1. $past Startup History Hole  [Medium]
    2. $rose Sampled on Clock Edge  [Medium]
    3. $fell Is an Event, Not a Level  [Easy]
    4. $stable Repeated Hold Check  [Medium]
    5. $past After Reset Release  [Medium]
    6. Vector $rose Sampling Trap  [Hard]

    Work each puzzle before reading the solution: predict the exact output or answer, name the rule that governs it, then check yourself.

    Related topics

    • SVA Assertion Puzzles section

    • VLSI DV Interview Puzzles hub

    PreviousNext: $past Startup History Hole

    Up next

    Up next$past Startup History Hole

    Sign in to save progress

    Practice this lessonPrevious lessonReport an error

    See also

    • Sequence Puzzles
    • Implication Puzzles
    • Assertion Debug Puzzles