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Course contents

  • Start Here5
  • SystemVerilog Language Foundations28
  • Object-Oriented SystemVerilog for Verification30
  • Constraint Randomization — Interview-Critical Deep Dive39
  • SystemVerilog Assertions — Interview-Critical Deep Dive41
  • Functional Coverage in SystemVerilog25
  • Testbench Architecture in SystemVerilog24
  • Advanced Language & Integration26
  • Senior & Interview Preparation23
    • Senior Debug Playbook
    • Reviewing Verification Code
    • Verification Strategy: Spec to Sign-Off
    • SystemVerilog Interview Q&A Bank
      • Q&A: Language Core
      • Q&A: Testbench Plumbing
      • Q&A: Classes and Interfaces
      • Q&A: Constraint and Assertion Fire-Drill
      • Q&A: Scenario and Design Questions
    • Capstone: Verify a Parameterized FIFO
  • Principal-Level Verification34
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←SystemVerilog Interview Q&A Bank
  1. Topics
  2. SystemVerilog
  3. Senior & Interview Preparation
  4. SystemVerilog Interview Q&A Bank
  5. Q&A: Constraint and Assertion Fire-Drill
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    Part 8 of 9, lesson 16 of 23Part 8 of 9/Senior & Interview Prep/Lesson 16 of 23Intermediate

    Q&A: Constraint and Assertion Fire-Drill

    Revision: fast map for constraint and SVA fluency, with one-line answers and links to the dedicated drills topics.

    This page is a revision map, not a second source. Each answer below is the ten-second version; the solver math and the sequence depth live in the drills topics and the lessons they link to.

    A revision map, not a second source

    If the interviewer asks

    Revise in

    Even values, dist weights, soft, solve-before, with, randc

    Randomization interview drills

    Overlapping versus non-overlapping implication, vacuity, repetition, past values, reset handling

    SVA interview drills

    What coverage proves and when it closes

    Coverage closure

    Constraint one-liners you must recite

    Q: Even values, aligned values, how do you constrain them

    Zero the low bits: addr[0] == 1'b0 for even, addr[1:0] == 2'b00 for multiples of four. Multiples of 2 to the N have N low zeros. See Even/Odd, Alignment & Divisibility.

    Q: Assign-weight versus divide-weight in dist, what changes

    := weights each value in the range; :/ shares one weight across the range. Both forms also define the legal set: unlisted values can never generate. See dist: Weighted Distributions.

    Q: Soft constraints, when do they lose

    A soft constraint is a default the solver drops silently whenever a hard constraint contradicts it. See soft Constraints.

    Q: Solve-before, what does it change

    Only the distribution, never the legal set. See Implication, if/else and solve...before.

    Q: Inline with-blocks and random-cyclic

    A with block adds one-call hard constraints, and names resolve to the object first, so local:: reaches the test scope. See Inline Constraints. randc permutes through every legal value once per cycle and fits small fields only. See rand vs randc.

    design.sv
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    // snippet
    // rand bit [7:0] addr;
    // constraint c_even { addr[0] == 1'b0; }
    // constraint c_len  { len dist { 1 := 50, [2:9] := 5 }; }
    // constraint c_dflt { soft len inside {[1:8]}; }
    // constraint c_ord  { solve err before code; }
    // assert(t.randomize() with { len == local::len; });
    // randc bit [1:0] chan;   // cycles 0,1,2,3 in a fresh order

    Assertion one-liners you must recite

    Q: Overlapping versus non-overlapping implication

    |-> starts the consequent the same cycle the antecedent completes; |=> waits one cycle, and a |=> b equals a |-> ##1 b. Registered responses need the non-overlapping form. See |-> vs |=>.

    Q: Vacuous passes, why are they dangerous

    An implication passes vacuously whenever its antecedent never matches, checking nothing. Put a cover on every antecedent and audit it at closure. See Vacuous Success.

    Q: Repetition flavors, past values and reset

    [*N] needs N back-to-back cycles, [->N] lands exactly on the Nth occurrence, and [=N] has a floating endpoint. See Repetition. Before N ticks of history exist $past returns the type default, so gate the opening cycles. See $past. disable iff aborts in-flight attempts asynchronously.

    design.sv
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    // snippet
    // a_same: assert property (@(posedge clk) req |-> gnt);
    // a_next: assert property (@(posedge clk) req |=> gnt);
    // c_req:  cover property (@(posedge clk) req);
    // a_burst: assert property (@(posedge clk) start |-> (beat [->3]) ##1 done);
    // a_stable: assert property (@(posedge clk) disable iff (!rst_n)
    //   (valid && !ready) ##1 valid |-> data == $past(data));

    What coverage proves

    Three checkers divide the work: the scoreboard catches data and ordering bugs, assertions catch cycle-accurate protocol violations, and coverage proves what was exercised. Coverage catches nothing by itself, and a cover on every assertion antecedent turns vacuity into a number. See Sign-Off Metrics and Review.

    A dist that never lists a value can never generate it. Chaining ##1 after [=N] anchors to a floating endpoint. Both read as stimulus or assertion bugs when they are really specification slips.

    The solve-before marker is one sentence: same solution set, different probability. Say it first, then give the rare-flag example.

    Check yourself len dist { 1 := 50, [2:9] := 5 }: what weight does each value from 2 to 9 carry, and can 10 generate?

    Each carries weight 5, and 10 can never generate. The dist defines the legal set as well as the weights.

    Check yourself A green assertion never saw its antecedent fire. What did it verify?

    Nothing. The passes are vacuous, which is why every assert ships with a cover on its antecedent.

    Related topics

    • Randomization interview drills

    • SVA interview drills

    • Coverage: covergroup basics

    • Coverage: closure

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    See also

    • Q&A: Language Core
    • Q&A: Testbench Plumbing