Engineers with about seven years of experience, or anyone who has finished Senior and Interview Prep and wants the patterns that scale beyond one block. It is not a first read of SystemVerilog.
I can explain why a scoreboard for out-of-order traffic needs one queue per ordering key, and not one global FIFO or an any-order search.
I can turn a spec into plan rows that each name a stimulus, a checker, a coverage item and a done criterion.
I can write an assertion that follows one transaction from request to response, with a local variable or an equivalent counter.
Comfortable with all three: start at the first topic. Hesitating on any: finish Parts 7 and 8 first, then return here.
Engineers with seven or more years are judged on how they verify systems, not on syntax. This part covers the patterns that scale: reusable testbench architecture, checking for multi-outstanding traffic, assertions that track IDs, coverage of real features, and the judgment calls a lead makes.
It assumes Parts 1 to 8. UVM is built from the same patterns; the UVM course shows the library versions.
Topic | Path | Lessons | What it covers | Time |
|---|---|---|---|---|
Recommended | 5 | Policy classes, abstract BFMs, parameterized interfaces, interface classes and layered stimulus. | 45 min | |
Required | 5 | ID-tagged and multi-stream scoreboards, drain and leak accounting with a runnable leak-and-hang bench, and memory-model checkers. | 50 min | |
Recommended | 5 | Abort operators, recursive properties, let and libraries, ID tracking with local variables, formal-ready assertions. | 45 min | |
Recommended | 4 | Transaction and temporal coverage, filtered bins, assertion-backed covers and closure at scale. | 35 min | |
Required | 10 | Spec, environment, checking, coverage, a six-bug hunt and sign-off for an ID-tagged controller, in ten lessons. | 90 min | |
Recommended | 5 | Escaped bugs, intermittent failures, misleading metrics, scaling, and system design interviews. | 45 min |
Path says how much of each topic a first pass needs. Required: core for this part's goal, read it. Recommended: most learners should read it. Optional: reference, specialist or revision material; skip it on a first pass and return when you need it. Lesson-level labels are on each topic page.
ID-Tagged Scoreboard and Memory-Model Checker: the checking rules everything else leans on.
Abstract BFM and Local Variables for IDs: the two patterns the capstone uses most.
The capstone, pages 1, 3, 5, 7 and 9 first.
Abort Operators, Recursive Properties, Interface Classes and Policy Classes: optional, each with its prerequisites at the top.
Scaling Verification and System Design Interviews: when a project or an interview needs them. The second is revision practice.
The even-numbered capstone pages (benches that prove the page before) when you want to run and break the code yourself.
Five questions across the part. Each answer names the lesson that teaches it; if you cannot answer, go back there.
Hide the virtual interface behind an abstract class whose implementation lives inside the interface, where the parameters are in scope. The environment then holds a class handle and no width. Abstract BFM builds it; Parameterized Interfaces shows the simpler option for one width change.
One that only checks that every expected item eventually arrives, in any order. Responses must stay in order within an ID even when IDs interleave. The ID-Tagged Scoreboard lesson builds one queue per ID.
Each started attempt holds its own copy of the ID, ticket and data, so attempts overlap without interfering. If the expected data is read from the design's own memory, it checks order and identity but cannot see data bugs. Local Variables for IDs teaches the technique; the capstone Checking page shows the limit.
The coverage model may measure what the stimulus or RTL does rather than the features in the spec, and a checker may be blind to the symptom. Metrics That Lie covers both; Transaction and Temporal Coverage shows how to model derived state instead of raw signals.
Script the faults the spec forbids plus one legal case that must stay silent, and require the right checker to fire for each; then plant bugs in the design and record which checker caught which. Testing the Checkers and Bug Hunt Results and Sign-Off do both.