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Course contents

  • Start Here5
  • SystemVerilog Language Foundations28
  • Object-Oriented SystemVerilog for Verification30
  • Constraint Randomization — Interview-Critical Deep Dive39
  • SystemVerilog Assertions — Interview-Critical Deep Dive41
  • Functional Coverage in SystemVerilog25
    • Covergroups & Coverpoints
    • Bins: Explicit, Auto, Illegal & Ignore
    • Cross Coverage
    • Coverage Options & Methods
    • Coverage Closure & Sign-Off
  • Testbench Architecture in SystemVerilog24
  • Advanced Language & Integration26
  • Senior & Interview Preparation23
  • Principal-Level Verification34
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←SystemVerilog
  1. Topics
  2. SystemVerilog
  3. Functional Coverage in SystemVerilog
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    Part 5 of 9Part 5 of 9/Functional CoverageIntermediate

    Functional Coverage in SystemVerilog

    Covergroups, coverpoints, bins, crosses, options, and the closure workflow — measuring what your testbench actually exercised.

    • 5topics
    • 25lessons

    Functional coverage measures scenarios from the specification, while code coverage measures structure from the RTL. This part builds covergroups, bins and crosses, then closes the loop from holes to sign-off.

    Closure in one page: Coverage Closure & Sign-Off shows the whole loop on one page: plan from the spec, run, find the holes, fix each one, sign off with evidence. You can read it first, then come back to build the parts.

    Learning path through the coverage topics.
    Suggested order. Covergroups first, so every later bin and cross has a structure to fill.

    The five topics

    Topic

    Path

    Lessons

    What it covers

    Time

    Covergroups & Coverpoints

    Required

    7

    Structure, sampling, expressions, a first model with a real report, and the bins model the benches count with.

    45 min

    Bins: Explicit, Auto, Illegal & Ignore

    Required

    4

    Bins turn sampled values into named scenarios, violations and exclusions.

    30 min

    Cross Coverage

    Recommended

    5

    Cross coverage from product bins to spec-driven patterns, with pruning and explosion control.

    40 min

    Coverage Options & Methods

    Optional

    4

    Per-instance options, weights, goals, sampling methods and covergroup arguments.

    30 min

    Coverage Closure & Sign-Off

    Required

    5

    Triage holes, steer stimulus, waive the unreachable, and sign off with evidence.

    40 min

    Required is the core first pass for this part. Recommended is for most learners. Optional is reference, a specialist topic or revision.

    Learn now

    • Your First Coverage Model: three bins and a report that names the hole.

    • Auto Bins vs Explicit Bins and Exclusions, Patterns & Filters: what a bin says, and what an exclusion can hide.

    • Cross Basics: why two full coverpoints do not make a full cross.

    • Hole Analysis and Triage: what to do with a hole.

    Return to later

    • Options and methods: Instance Options, Coverage Methods and Parameterizing Covergroups, when a report has several instances. Weights, Goals & at_least is worth a read when a goal is not 100.

    • Cross Coverage Patterns and Bin Design Strategy, when you design a model for a real block.

    • Sign-Off Needs Both and the waiver and sign-off lessons, before a review.

    Running the lessons on open tools

    The open simulators do not count covergroups: Verilator 5.048 ignores the bins and Icarus 13 has none. The lessons teach the real covergroup syntax and count with The Bins Model, a small set of plain classes that prints a simulator-shaped report. Its page lists the source and maps each method to the covergroup syntax it stands for.

    Illegal and ignore bins can hide bugs. An ignored value is dropped without a trace, and an illegal bin that nobody reads is only a log line. Review every exclusion like code, and see the cautions in the Bins and Cross lessons.

    Before moving on

    Check yourself A suite reports full code coverage but misses a required scenario. Why?

    Code coverage records which lines, branches and toggles ran. Only a covergroup with a planned bin records that a specified scenario happened. Taught in Sign-Off Needs Both: Code and Functional Coverage.

    Check yourself A coverpoint on an 8-bit length field uses auto bins and reads 100%, but length 0 was never sent. How?

    With many values, auto bins share buckets, so hits on 1, 2 or 3 can fill the bucket that also holds 0. Name the value in its own bin. Taught in Auto Bins vs Explicit Bins.

    Check yourself Both coverpoints read 100% and the cross reads 60%. Is the cross covered?

    No. Each point proves its values occurred somewhere, not in the same sample. The cross counts combinations. Taught in Cross Basics.

    Check yourself Four ports share one covergroup and the number reads 98%. Why might one port still be untested?

    The type-level number merges the instances, so three busy ports hide an idle fourth. Per-instance rows show each one. Taught in option.per_instance & Instance Options.

    Check yourself Regression sits at 90% a week before tape-out. What do you ask first about a hole?

    Whether the bin itself is right, then whether the hole is reachable, before writing any test or exclusion. Taught in Hole Analysis and Triage.

    Related topics

    • Previous: SVA

    • Next: Testbench

    • Back to the course overview

    PreviousNext: Covergroups & Coverpoints

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    See also

    • Start Here
    • SystemVerilog Language Foundations
    • Object-Oriented SystemVerilog for Verification