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Course contents

  • Start Here5
  • SystemVerilog Language Foundations28
  • Object-Oriented SystemVerilog for Verification30
  • Constraint Randomization — Interview-Critical Deep Dive39
  • SystemVerilog Assertions — Interview-Critical Deep Dive41
  • Functional Coverage in SystemVerilog25
  • Testbench Architecture in SystemVerilog24
  • Advanced Language & Integration26
  • Senior & Interview Preparation23
    • Senior Debug Playbook
    • Reviewing Verification Code
      • Reviewing Transactions & Constraints
      • Reviewing TB Components
      • Reviewing Assertions & Coverage
      • Review Process & Checklist
    • Verification Strategy: Spec to Sign-Off
    • SystemVerilog Interview Q&A Bank
    • Capstone: Verify a Parameterized FIFO
  • Principal-Level Verification34
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←Senior & Interview Preparation
  1. Topics
  2. SystemVerilog
  3. Senior & Interview Preparation
  4. Reviewing Verification Code

Part 8 of 9Part 8 of 9/Senior & Interview PrepIntermediate

Reviewing Verification Code

Testbenches fail by passing: checklists for stimulus, components, assertions, and review process.

  • 4topics
  • 4lessons

Verification code review has a different failure cost than design review. A sloppy RTL block fails in simulation, but a sloppy testbench fails by passing: it stops checking, and nobody notices until silicon.

Three questions carry every review in this topic. Can this constraint set hide a legal-but-nasty case. Can this scoreboard compare nothing and report green. Can this assertion pass without ever firing.

Diagram
REVIEW PASSES — order matters: architecture before syntax

  pull request arrives
       |
       v
  PASS 1 — INTENT
  what is this change for, and does the approach fit the env
  (wrong approach: stop and talk, not forty nits)
       |
       v
  PASS 2 — CHECKING INTEGRITY
  transactions: reachability, checked randomize, copy and compare
  components:   timing, reset, item_done, drain, fork hygiene
  assertions:   vacuity, reset gating, bounds, bin intent
       |
       v
  PASS 3 — MAINTAINABILITY
  naming, duplication, magic numbers, comments that lie
       |
       v
  verdict: approve, approve with notes, or request changes
  (block only on correctness and architecture; note the rest)

Lesson

What you review

Path

Reviewing Transactions & Constraints

Reachability of the stimulus space, checked randomize calls, complete copy and compare.

Recommended

Reviewing TB Components

Driver timing and reset, monitor source of truth, scoreboard drain, fork hygiene.

Recommended

Reviewing Assertions & Coverage

Vacuous passes, reset gating, liveness bounds, bins with plan intent.

Recommended

Review Process & Checklist

The three-pass method, comments that land, and the master checklist by artifact.

Required

Path: Required is the core first pass for this topic, Recommended is what most learners should read, and Optional is reference, specialist or revision material you can skip at first.

Check yourself A scoreboard reports zero mismatches on a 260-transaction regression. Which two numbers decide whether that result means anything?

The compare count and the leftover expected-queue depth. Zero compares, or a nonempty queue, means the green result checked nothing.

“How do you review a testbench” is a senior staple. The strong answer names the fails-by-passing asymmetry, then walks one artifact: constraints, components, or assertions.

PreviousNext: Reviewing Transactions & Constraints

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See also

  • Senior Debug Playbook
  • Verification Strategy: Spec to Sign-Off
  • SystemVerilog Interview Q&A Bank